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LTC2293/LTC2292/LTC2291
Dual 12-Bit, 65/40/25Msps
Low Power 3V ADCs
FEATURES
DESCRIPTIO
■ Integrated Dual 12-Bit ADCs
The LTC®2293/LTC2292/LTC2291 are 12-bit 65Msps/
■ Sample Rate: 65Msps/40Msps/25Msps
40Msps/25Msps, low power dual 3V A/D converters de-
■ Single 3V Supply (2.7V to 3.4V)
signed for digitizing high frequency, wide dynamic range
■ Low Power: 400mW/235mW/150mW
signals. The LTC2293/LTC2292/LTC2291 are perfect for
■ 71dB SNR up to 70MHz Input
demanding imaging and communications applications
■ 85dB SFDR up to 70MHz Input
with AC performance that includes 71dB SNR and 85dB
■ 110dB Channel Isolation at 100MHz
SFDR for signals well beyond the Nyquist frequency.
■ Multiplexed or Separate Data Bus
■ Flexible Input: 1VP-P to 2VP-P Range
■ 575MHz Full Power Bandwidth S/H
■ Clock Duty Cycle Stabilizer
DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSBRMS.
■ Shutdown and Nap Modes
A single 3V supply allows low power operation. A separate
■ Pin Compatible Family
output supply allows the outputs to drive 0.5V to 3.3V
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
logic. An optional multiplexer allows both channels to
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
share a digital output bus.
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
A single-ended CLK input controls converter operation. An DataShee
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
optional clock duty cycle stabilizer allows high perfor-
10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit) DataSheet4mUa.cnocme at full speed for a wide range of clock duty cycles.
■ 64-Pin (9mm × 9Umm) QFN Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
All other trademarks are the property of their respective owners.
■ Wireless and Wired Broadband Communication
■ Imaging Systems
■ Spectral Analysis
■ Portable Instrumentation
TYPICAL APPLICATIO
ANALOG
INPUT A
+
INPUT
S/H
–
CLK A
CLK B
CLOCK/DUTY CYCLE
CONTROL
CLOCK/DUTY CYCLE
CONTROL
ANALOG
INPUT B
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+
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
12-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
OVDD
D11A
•••
D0A
OGND
MUX
OUTPUT
DRIVERS
OVDD
D11B
•••
D0B
OGND
229321 TA01
LTC2293: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
72
71
70
69
68
0
50 100 150
INPUT FREQUENCY (MHz)
200
229321 TA02
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LTC2293/LTC2292/LTC2291
ABSOLUTE AXI U RATI GS
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation ............................................ 1500mW
Operating Temperature Range
LTC2293C, LTC2292C, LTC2291C ........... 0°C to 70°C
LTC2293I, LTC2292I, LTC2291I ..........–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
UW U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
AINA+ 1
AINA– 2
REFHA 3
48 DA5
47 DA4
46 DA3
REFHA 4
45 DA2
REFLA 5
44 DA1
REFLA 6
43 DA0
VDD 7
42 NC
CLKA 8 65 41 NC
CLKB 9
40 OFB
VDD 10
REFLB 11
39 DB11
38 DB10
REFLB 12
37 DB9
REFHB 13
36 DB8
REFHB 14
AINB– 15
AINB+ 16
35 DB7
34 DB6
33 DB5
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UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 125°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB
ORDER PART
NUMBER
QFN PART*
MARKING
DataShee
DataSheet4U.comLTC2293CUP
LTC2293IUP
LTC2293UP
LTC2292UP
LTC2292CUP
LTC2291UP
LTC2292IUP
LTC2291CUP
LTC2291IUP
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
LTC2293
LTC2292
LTC2291
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Resolution
(No Missing Codes)
● 12 12 12
Bits
Integral Linearity Error Differential Analog Input (Note 5) ● –1.4 ±0.3 1.4 –1.4 ±0.3 1.4 –1.3 ±0.3 1.3
LSB
Differential
Linearity Error
Differential Analog Input
● –0.8 ±0.15 0.8 –0.7 ±0.15 0.7 –0.7 ±0.15 0.7
LSB
Offset Error
(Note 6)
● –12 ±2 12 –12 ±2 12 –12 ±2 12
mV
Gain Error
External Reference
● –2.5 ±0.5 2.5 –2.5 ±0.5 2.5 –2.5 ±0.5 2.5
%FS
Offset Drift
±10 ±10 ±10 µV/°C
Full-Scale Drift
Internal Reference
±30 ±30 ±30 ppm/°C
External Reference
±15 ±15 ±15 ppm/°C
Gain Matching
External Reference
±0.3 ±0.3 ±0.3 %FS
Offset Matching
±2 ±2 ±2 mV
DataSheeTt4raUns.ictioonmNoise
SENSE = 1V
0.25 0.25 0.25 LSBRMS
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