PHT8N06LT 반도체 회로 부품 판매점
TrenchMOS transistor Logic level FET
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 NXP Semiconductors |
Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHT8N06LT
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection. It is intended for use in
DC-DC converters and general
purpose switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
MAX.
55
7.5
1.8
150
80
PINNING - SOT223
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
PIN CONFIGURATION
4
123
SYMBOL
d
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
ID
ID
IDM
Ptot
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Total power dissipation
Storage & operating temperature
-
RGS = 20 kΩ
-
Tsp = 25 ˚C
On PCB in Fig.2
Tamb = 25 ˚C
On PCB in Fig.2
Tamb = 100 ˚C
Tsp = 25 ˚C
Tsp = 25 ˚C
On PCB in Fig.2
Tamb = 25 ˚C
-
ESD LIMITING VALUE
SYMBOL
VC
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
13
7.5
3.5
2.2
40
8.3
1.8
150
UNIT
V
V
V
A
A
A
A
W
W
˚C
MIN.
-
MAX.
2
UNIT
kV
January 1998
1
Rev 1.100
Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHT8N06LT
THERMAL RESISTANCES
SYMBOL
Rth j-sp
Rth j-amb
PARAMETER
From junction to solder point
From junction to ambient
CONDITIONS
Mounted on any PCB
Mounted on PCB of Fig.17
TYP.
12
-
MAX.
15
70
UNIT
K/W
K/W
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS(TO)
IDSS
IGSS
±V(BR)GSS
RDS(ON)
Drain-source breakdown
VGS = 0 V; ID = 0.25 mA
voltage
Tj = -55˚C
Gate threshold voltage
VDS = VGS; ID = 1 mA
Tj = 150˚C
Tj = -55˚C
Zero gate voltage drain current VDS = 55 V; VGS = 0 V;
Tj = 150˚C
Gate source leakage current VGS = ±5 V
Tj = 150˚C
Gate source breakdown voltage IG = ±1 mA
Drain-source on-state
VGS = 5 V; ID = 5 A
resistance
Tj = 150˚C
MIN.
55
50
1.0
0.6
-
-
-
-
-
10
-
-
TYP.
-
-
1.5
-
-
0.05
-
0.02
-
-
65
-
MAX.
-
-
2.0
-
2.3
10
100
1
5
-
80
148
UNIT
V
V
V
V
V
µA
µA
µA
µA
V
mΩ
mΩ
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER
gfs
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td on
tr
td off
tf
Forward transconductance
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
CONDITIONS
VDS = 25 V; ID = 5 A; Tj = 25˚C
ID = 7 A; VDD = 44 V; VGS = 5 V
VGS = 0 V; VDS = 25 V; f = 1 MHz
VDD = 30 V; ID = 7 A;
VGS = 5 V; RG = 10 Ω;
Tj = 25˚C
MIN.
4
-
-
-
-
-
-
-
-
-
-
TYP.
-
11.2
2.2
5
500
110
60
10
30
30
30
MAX.
-
-
-
-
650
135
85
15
50
45
40
UNIT
S
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = -55 to 175˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
IDR
Continuous reverse drain
Tsp = 25˚C
current
IDRM Pulsed reverse drain current Tsp = 25˚C
VSD Diode forward voltage
IF = 5 A; VGS = 0 V
trr Reverse recovery time IF = 5 A; -dIF/dt = 100 A/µs;
Qrr
Reverse recovery charge
VGS = -10 V; VR = 30 V
MIN. TYP. MAX. UNIT
- - 7.5 A
- - 40 A
- 0.85 1.1 V
- 38 - ns
- 0.2 - µC
January 1998
2
Rev 1.100
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PHT8N06LT transistor
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