IDT29FCT53BP 반도체 회로 부품 판매점
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
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 Integrated Device |
®
Integrated Device Technology, Inc.
FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS
IDT29FCT52A/B/C
IDT29FCT53A/B/C
FEATURES:
• Equivalent to AMD’s Am2952/53 and National’s
29F52/53 in pinout/function
• IDT29FCT52A/53A equivalent to FAST™ speed
• IDT29FCT52B/53B 25% faster than FAST
• IDT29FCT52C/53C 37% faster than FAST
• IOL = 64mA (commercial) and 48mA (military)
• IIH and IIL only 5µA max.
• CMOS power levels (2.5mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Available in 24-pin DIP, SOIC, 28-pin LCC with JEDEC
standard pinout
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT29FCT52A/B/C and IDT29FCT53A/B/C are 8-bit
registered transceivers manufactured using an advanced
dual metal CMOS technology. Two 8-bit back-to-back regis-
ters store data flowing in both directions between two bidirec-
tional buses. Separate clock, clock enable and 3-state output
enable signals are provided for each register. Both A outputs
and B outputs are guaranteed to sink 64mA.
The IDT29FCT52A/B/C is a non-inverting option of the
IDT29FCT53A/B/C.
FUNCTIONAL BLOCK DIAGRAM(1)
CPA
CEA
A0
A1
A2
A3
A4
A5
A6
A7
D0 CE CP Q0
D1 Q1
D2 Q2
D3 A Q3
D4 Reg. Q4
D5 Q5
D6 Q6
D7 Q7
OEB
B0
B1
B2
B3
B4
B5
B6
B7
OEA
NOTE:
1. IDT29FCT52 function is shown.
Q0 D0
Q1 D1
Q2 D2
Q3 B D3
Q4 Reg. D4
Q5 D5
Q6 D6
Q7 CE CP D7
CPB
CEB
2533 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
7.1
MAY 1992
DSC-4605/3
1
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
B7
B6
B5
B4
B3
B2
B1
B0
OEB
CPA
CEA
GND
1 24
2 23
3 22
4 P24-1, 21
5 D24-1, 20
6
E24-1
&
19
7 SO24-2 18
8 17
9 16
10 15
11 14
12 13
Vcc
A7
A6
A5
A4
A3
A2
A1
A0
OEA
CPB
CEB
INDEX
B4
B3
B2
NC
B1
B0
OEB
4 3 2 28 27 26
5 1 25
6 24
7 23
8
L28-1
22
9 21
10 20
11 19
12 13 14 15 16 17 18
A5
A4
A3
NC
A2
A1
A0
DIP/CERPACK/SOIC
TOP VIEW
LCC
TOP VIEW
2533 drw 02
PIN DESCRIPTION
Name I/O
Description
A0-7 I/O Eight bidirectional lines carrying the A Register inputs or B Register outputs.
B0-7 I/O Eight bidirectional lines carrying the B Register inputs or A Register outputs.
CPA I Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal.
CEA I Clock Enable for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH
transition of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal
transitions.
OEB I Output Enable for the A Register. When OEB is LOW, the A Register outputs are enabled onto the B0-7 lines. When
OEB is HIGH, the B0-7 outputs are in the high-impedance state.
CPB I Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition
of the CPB signal.
CEB I Clock Enable for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH
transition of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal
transitions.
OEA I Output Enable for the B Register. When OEA is LOW, the B Register outputs are enabled onto the A0-7 lines. When
OEA is HIGH, the A0-7 outputs are in the high-impedance state.
2533 tbl 01
REGISTER FUNCTION TABLE(1)
(Applies to A or B Register)
Inputs
Internal
D CP CE Q
X X H NC
L↑LL
H↑ LH
Function
Hold Data
Load Data
2533 tbl 02
OUTPUT CONTROL(1)
Internal
Y-Outputs
OE Q
52 53
HX ZZ
LL LH
LHHL
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
NC = No Change
↑ = LOW-to-HIGH Transition
Function
Disable Outputs
Enable Outputs
2533 tbl 03
7.1 2
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IDT29FCT53BP transceiver
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