AD9371 반도체 회로 부품 판매점
Dual RF Transceiver
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 Analog Devices |
Data Sheet
Integrated, Dual RF Transceiver
with Observation Path
AD9371
FEATURES
Dual differential transmitters (Tx)
Dual differential receivers (Rx)
Observation receiver (ORx) with 2 inputs
Sniffer receiver (SnRx) with 3 inputs
Tunable range: 300 MHz to 6000 MHz
Tx synthesis bandwidth (BW) to 250 MHz
Rx BW: 8 MHz to 100 MHz
Supports frequency division duplex (FDD) and time division
duplex (TDD) operation
Fully integrated independent fractional-N radio frequency (RF)
synthesizers for Tx, Rx, ORx, and clock generation
JESD204B digital interface
APPLICATIONS
3G/4G micro and macro base stations (BTS)
3G/4G multicarrier picocells
FDD and TDD active antenna systems
Microwave, nonline of sight (NLOS) backhaul systems
GENERAL DESCRIPTION
The AD9371 is a highly integrated, wideband RF transceiver
offering dual channel transmitters and receivers, integrated
synthesizers, and digital signal processing functions. The IC
delivers a versatile combination of high performance and low
power consumption required by 3G/4G micro and macro BTS
equipment in both FDD and TDD applications. The AD9371
operates from 300 MHz to 6000 MHz, covering most of the
licensed and unlicensed cellular bands. The IC supports receiver
bandwidths up to 100 MHz. It also supports observation receiver
and transmit synthesis bandwidths up to 250 MHz to
accommodate digital correction algorithms.
The transceiver consists of wideband direct conversion signal
paths with state-of-the-art noise figure and linearity. Each complete
receiver and transmitter subsystem includes dc offset correction,
quadrature error correction (QEC), and programmable digital
filters, eliminating the need for these functions in the digital
baseband. Several auxiliary functions such as an auxiliary analog-
to-digital converter (ADC), auxiliary digital-to-analog converters
(DACs), and general-purpose input/outputs (GPIOs) are integrated
to provide additional monitoring and control capability.
An observation receiver channel with two inputs is included to
monitor each transmitter output and implement interference
mitigation and calibration applications. This channel also connects
to three sniffer receiver inputs that can monitor radio activity in
different bands.
Rev. A
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RX1+
RX1–
RX2+
RX2–
RX_EXTLO+
RX_EXTLO–
TX1+
TX1–
TX2+
TX2–
FUNCTIONAL BLOCK DIAGRAM
AD9371
RX1
RX2
LPF
LPF
ADC
ADC
EXTERNAL
OPTION
LO
GENERATOR
RF
SYNTHESIZER
DECIMATION,
pFIR,
DC OFFSET
QEC,
TUNING,
RSSI,
OVERLOAD
MICRO-
CONTROLLER
TX1
TX2
LPF
LPF
DAC
DAC
SPI
PORT
pFIR,
QEC,
INTERPOLATION
TX_EXTLO+
TX_EXTLO–
EXTERNAL
OPTION
LO
GENERATOR
LO
GENERATOR
RF
SYNTHESIZER
RF
SYNTHESIZER
ORX1+
ORX1–
ORX2+
ORX2–
OBSERVATION
Rx
GPIO
AUXADC
AUXDAC
CLOCK
GENERATOR
SNRXA+
SNRXA–
SNRXB+
SNRXB–
SNRXC+
SNRXC–
SNIFFER
Rx
LPF DECIMATION,
ADC
pFIR,
AGC,
DC OFFSET,
LPF QEC,
ADC
TUNING,
RSSI,
OVERLOAD
NOTES
1. FOR JESD204B PINS, SEE FIGURE 4.
Figure 1.
The high speed JESD204B interface supports lane rates up to
6144 Mbps. Four lanes are dedicated to the transmitters and four
lanes are dedicated to the receiver and observation receiver channels.
The fully integrated phase-locked loops (PLLs) provide high
performance, low power fractional-N frequency synthesis for
the transmitter, the receiver, the observation receiver, and the
clock sections. Careful design and layout techniques provide the
isolation demanded in high performance base station applications.
All voltage controlled oscillator (VCO) and loop filter components
are integrated to minimize the external component count.
A 1.3 V supply is required to power the core of the AD9371, and
a standard 4-wire serial port controls it. Other voltage supplies
provide proper digital interface levels and optimize transmitter
and auxiliary converter performance. The AD9371 is packaged in a
12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9371
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Current and Power Consumption Specifications..................... 9
Timing Specifications ................................................................ 11
Absolute Maximum Ratings.......................................................... 13
Reflow Profile.............................................................................. 13
Thermal Resistance .................................................................... 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions........................... 14
Typical Performance Characteristics ........................................... 17
700 MHz Band ............................................................................ 17
2.6 GHz Band.............................................................................. 27
3.5 GHz Band.............................................................................. 37
REVISION HISTORY
11/2016—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 6
Changes to Table 2............................................................................ 9
Changes to L3, L4 Description Column, Table 6; M3, M4
Description Column, Table 6; and M13, M14 Description
Column, Table 6.............................................................................. 16
Changes to Figure 46 Caption....................................................... 23
Changes to Figure 48 Caption....................................................... 24
Changes to Figure 56 Caption and Figure 57 Caption .............. 25
Changes to Figure 82 Caption....................................................... 30
Changes to Figure 105 Caption .................................................... 33
Changes to Figure 107 Caption .................................................... 34
Changes to Figure 115 Caption and Figure 116 Caption .......... 35
Changes to Figure 141 Caption .................................................... 40
Changes to Figure 164 Caption .................................................... 43
Changes to Figure 166 Caption .................................................... 44
Changes to Figure 174 Caption and Figure 175 ......................... 45
Changes to Figure 194 and Figure 199 Caption ......................... 49
Changes to Figure 222 Caption .................................................... 53
Changes to Figure 224 Caption .................................................... 54
Added Figure 230 to Figure 235; Renumbered Sequentially .... 55
Added Figure 236 to Figure 239 ................................................... 56
Added External LO Inputs Section .............................................. 58
7/2016—Revision 0: Initial Version
Data Sheet
5.5 GHz Band.............................................................................. 47
Theory of Operation ...................................................................... 57
Transmitter (Tx) ......................................................................... 57
Receiver (Rx)............................................................................... 57
Observation Receiver (ORx)..................................................... 57
Sniffer Receiver (SnRx) ............................................................. 57
Clock Input.................................................................................. 57
Synthesizers................................................................................. 58
Serial Peripheral Interface (SPI) Interface .............................. 58
GPIO_x AND GPIO_3P3_x Pins ............................................ 58
Auxiliary Converters.................................................................. 58
JESD204B Data Interface .......................................................... 58
Power Supply Sequence ............................................................. 59
JTAG Boundary Scan................................................................. 59
Outline Dimensions ....................................................................... 60
Ordering Guide .......................................................................... 60
Rev. A | Page 2 of 60
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