MC74HCT373A 반도체 회로 부품 판매점
Octal 3-State Noninverting Transceiver Latch
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 Motorola Semiconductors |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Noninverting
Transparent Latch with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC54/74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT373A is identical in pinout to the LS373.
The eight latches of the HCT373A are transparent D–type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs. When
Latch Enable is taken low, data meeting the setup and hold times
becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high–impedance state.
Thus, data may be latched even when the outputs are not enabled.
The HCT373A is identical in function to the HCT573A, which has the
input pins on the opposite side of the package from the output pins. This
device is similar in function to the HCT533A, which has inverting outputs.
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS–Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 196 FETs or 49 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
NONINVERTING
OUTPUTS
LATCH ENABLE 11
OUTPUT ENABLE 1
PIN 20 = VCC
PIN 10 = GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDesign Criteria
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Count*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Propagation Delay
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Power Dissipation
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSpeed Power Product
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Equivalent to a two–input NAND gate.
Value
49
1.5
5.0
.0075
Units
ea.
ns
µW
pJ
2/97
© Motorola, Inc. 1997
1
MC54/74HCT373A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
SD SUFFIX
SSOP PACKAGE
CASE 940C–03
20
1
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
ORDERING INFORMATION
MC54HCTXXXAJ
Ceramic
MC74HCTXXXAN
Plastic
MC74HCTXXXADW SOIC
MC74HCTXXXASD SSOP
MC74HCTXXXADT TSSOP
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
D0
1
2
3
20 VCC
19 Q7
18 D7
D1 4
17 D6
Q1 5
Q2 6
D2 7
16 Q6
15 Q5
14 D5
D3 8
13 D4
Q3 9
GND 10
12 Q4
11 LATCH
ENABLE
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable D
Q
L HH H
L HL L
L L X No Change
H XX Z
X = don’t care
Z = high impedance
REV 7
MC54/74HCT373A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
± 20
V
V
mA
DC Output Current, per Pin
± 35 mA
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
SSOP or TSSOP Package†
± 75
750
500
450
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Plastic DIP, SOIC, SSOP or TSSOP Package)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Ceramic DIP)
– 65 to + 150
260
300
_C
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC DC Supply Voltage (Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min Max Unit
4.5 5.5 V
0 VCC V
– 55 + 125 _C
0 500 ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
Parameter
Test Conditions
Minimum High–Level Input
Voltage
Maximum Low–Level Input
Voltage
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
Minimum High–Level Output
Voltage
vVin = VIH or VIL
|Iout| 20 µA
Maximum Low–Level Output
Voltage
vVin = VIH or VIL
|Iout| 6.0 mA
vVin = VIH or VIL
|Iout| 20 µA
Maximum Input Leakage Current
vVin = VIH or VIL
|Iout| 6.0 mA
Vin = VCC or GND
VCC
V
4.5
5.5
4.5
5.5
4.5
5.5
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
2.0 2.0 2.0
2.0 2.0 2.0
0.8 0.8 0.8
0.8 0.8 0.8
4.4 4.4 4.4
5.4 5.4 5.4
Unit
V
V
V
4.5 3.98
4.5 0.1
5.5 0.1
3.84
0.1
0.1
3.7
0.1
0.1
V
4.5 0.26
0.33
0.4
5.5 ± 0.1 ± 1.0 ± 1.0 µA
MOTOROLA
2 High–Speed CMOS Logic Data
DL129 — Rev 6
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MC74HCT373A transceiver
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관련 데이터시트
MC74HCT373A
Octal 3-State Noninverting Transceiver Latch - Motorola Semiconductors
MC74HCT373A
Octal 3-State Noninverting Transceiver Latch with LSTTL-Compatible Inputs - ON Semiconductor