EUP7998 반도체 회로 부품 판매점
Sink/Source DDR Termination Regulator
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 Eutech |
EUP7998
Sink/Source DDR Termination Regulator
DESCRIPTION
The EUP7998 is a high performance linear regulator
designed to provide power for termination of a DDR
memory bus. It significantly reduces parts count,
board space and overall system cost over previous
switching solutions.
The EUP7998 maintains a fast transient response
using only 20μF or 30μF output capacitance. The
EUP7998 supports a remote sensing function and all
power requirements for DDR, DDR2, DDR3 and
Low Power DDR3/DDR4 VTT bus termination.
The EUP7998 provides current and thermal limits to
prevent damage to the linear regulator. Additionally,
The EUP7998 generates an open-drain PGOOD
signal to monitor the output regulation. An active
high enable pin EN can pull VTT low, but REFOUT
will remain active. A power savings advantage can be
obtained in this mode through lower quiescent
current.
The EUP7998 is available in the 3mm × 3mm
TDFN-10 and SOP-8 (EP) packages.
FEATURES
z VLDOIN Input Voltage Range: 1.1V to 3.5V
z VIN Input Voltage Range: 2.375V to 5.5V
z Typically 3× 10μF MLCCs stable for DDR
z Fast Load-Transient Response
z ±10mA Buffered Reference (REFOUT)
z Meet DDR, DDR2 JEDEC Specifications.
Supports DDR3 and Low-Power DDR3/DDR4
VTT Applications
z Power-Good Window Comparator
z With Soft Start, UVLO and OCP
z Thermal Shutdown
z Available in 10-Pin 3mm× 3mm TDFN and
SOP-8 (EP) packages
z RoHS Compliant and 100% Lead(Pb)-Free
Halogen-Free
APPLICATIONS
z Notebook/Desktop/Server
z DDR Memory Termination
z Telecom/Datacom, GSM Base Station,
LCD-TV/PDP-TV, Copier/Printer, Set-Top Box
Typical Application Circuit
Figure 1. For TDFN-10 package
DS7998 Ver1.1 Aug. 2010
Downloaded from Elcodis.com electronic components distributor
1
http://www.Datasheet4U.com
Typical Application Circuit (continued)
EUP7998
Pin Configurations
Package
Type
Figure 2. For SOP-8(EP) package
Pin Configurations
Package
Type
Pin Configurations
TDFN-10
SOP-8
(EP)
Pin Description
PIN TDFN-10
REFIN
1
VLDOIN
2
VO 3
PGND
4
VOSNS
5
REFOUT
6
EN
GND
PGOOD
VIN
7
8
9
10
SOP-8 (EP)
1
2
3
9
(Thermal pad)
4
5
6
7
-
8
DESCRIPTION
External Reference Input
Power Supply of the LDO. Internally connected to the output source
MOSFET.
Output of the LDO
Power Ground
Voltage sense input for the LDO. Connect to positive terminal of the
output capacitor.
Buffered Reference Output. The output of the unity-gain reference input
buffer sources and sinks over 10mA. Bypass REFOUT to GND with a
0.1μF ceramic capacitor.
Enable Control Input. Active High Input. For DDR VTT application,
connect EN to SLP_S3.
Ground
Open-Drain Power-Good Output
Power Supply Input. Connect to the system supply voltage. Bypass VIN to
GND with a 1μF or 4.7μF ceramic capacitor.
Note(1):PGND, GND and thermal pad must be connected together outside under thermal pad.
DS7998 Ver1.1 Aug. 2010
2
Downloaded from Elcodis.com electronic components distributor
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제조업체: Eutech
( eutech )
EUP7998 regulator
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[ EUP7998.PDF ]
[ EUP7998 다른 제조사 검색 ]
국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈
( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )
전력반도체 문의 : 010-3582-2743
관련 데이터시트
EUP7996
1.5A DDR Termination Regulator - Eutech Microelectronics
EUP7998
Sink/Source DDR Termination Regulator - Eutech