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Hynix Semiconductor |
240pin Registered DDR2 SDRAM DIMMs based on 1Gb version C
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version C DDR2
SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb ver-
sion C based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width
form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
• JEDEC standard Double Data Rate2 Synchro-
nous DRAMs (DDR2 SDRAMs) with 1.8V +/-
0.1V Power Supply
• All inputs and outputs are compatible with
SSTL_1.8 interface
• 8 Bank architecture
• Posted CAS
• Programmable CAS Latency 3 , 4 , 5
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both
sequential and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60 ball(x4/x8)
• 133.35 x 30.00 mm form factor
• RoHS compliant
ORDERING INFORMATION
Part Name
HYMP112P72CP8-C4/Y5/S5/S6
HYMP125P72CP4-C4/Y5/S5/S6
HYMP151P72CP4-C4/Y5/S5/S6
HYMP112R72CP8-E3/C4
HYMP125R72CP4-E3/C4
HYMP151R72CP4-E3/C4
Density
1GB
2GB
4GB
1GB
2GB
4GB
Organization
128Mx72
256Mx72
512Mx72
128Mx72
256Mx72
512Mx72
# of
DRAMs
9
18
36
9
18
36
# of
ranks
1
1
2
1
1
2
Parity
Support
O
O
O
X
X
X
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Jun. 2007
1
1240pin Registered DDR2 SDRAM DIMMs
SPEED GRADE & KEY PARAMETERS
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
E3 (DDR2-400)
400
-
-
3-3-3
C4 (DDR2-533)
400
533
-
4-4-4
Y5 (DDR2-667)
400
533
667
5-5-5
S5 (DDR2-800)
400
533
800
5-5-5
Unit
Mbps
Mbps
Mbps
tCK
ADDRESS TABLE
Density Organization Ranks
1GB
2GB
4GB
128M x 72
256M x 72
512M x 72
1
1
2
SDRAMs
128Mb x 8
256Mb x 4
256Mb x 4
# of
DRAMs
9
18
36
# of row/bank/column Address
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)
Refresh
Method
8K / 64ms
8K / 64ms
8K / 64ms
Rev. 0.2 / Jun. 2007
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