HYMP112P72CP8L-S6 반도체 회로 부품 판매점
240pin DDR2 VLP Registerd DIMMs based on 1Gb C version
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 Hynix Semiconductor |
240pin DDR2 VLP Registerd DIMMs based on 1Gb C version
This Hynix DDR2 VLP(Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 1Gb C ver-
sion DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb C ver-
sion based VLP Registered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of
industry standard. It is suitable for easy interchange and addition.
ORDERING INFORMATION
Part Name
Density
Org.
Component Configuration
Ranks
Parity
Support
HYMP112P72CP8L-C4/Y5/S6
HYMP125P72CP4L-C4/Y5/S6
HYMP351P72CMP4L-C4/Y5/S6
HYMP41GP72CNP4L-C4/Y5
1GB
2GB
4GB
8GB
128Mbx72 128Mbx8(HY5PS1G821CFP)*9
256Mbx72 256Mbx4(HY5PS1G421CFP)*18
512Mbx72 512Mbx4(HY5PS2G421CMP)*18
1Gbx72 1Gbx4(HY5PS4G421CNP)*18
1
1
2
4
O
O
O
O
Note:
1. “P” of part number[12th digit] stands for Lead free products.
SPEED GRADE & KEY PARAMETERS
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
C4 (DDR2-533)
400
533
-
-
4-4-4
Y5 (DDR2-667)
400
533
667
-
5-5-5
S6 (DDR2-800)
-
400
533
800
6-6-6
Unit
Mbps
Mbps
Mbps
Mbps
tCK
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / May. 2008
1
Free Datasheet http://www.datasheet4u.com/
FEATURES
1240pin DDR2 VLP Registered DIMMs
• JEDEC standard 1.8V +/- 0.1V Power Supply
• VDDQ : 1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_1.8 interface
• 4 Bank architecture
• Posted CAS
• Programmable CAS Latency 3 , 4 , 5
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequential and interleave mode
• Average Auto Refresh Period 7.8us under TCASE 85 , 3.9us at 85 < TCASE 95
• High Temperature Self-Refresh Entry enablble features
• PASR(Partial Array Self- Refresh)
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA
• 133.35 x 18.29 mm form factor
• Lead-free Products are RoHS compliant
ADDRESS TABLE
Density Organization Ranks
SDRAMs
# of
DRAMs
# of row/bank/column Address
Refresh
Method
1GB 128Mb x 72 1 128Mb x 8
9
14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms
2GB
256Mb x 72
1
256Mb x 4
18 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
4GB
512Mb x 72
2
256Mb x 4
36 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64m
8GB
1Gb x 72
4 256Mb x 4 72 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64m
Rev. 0.2 / May. 2008
Free Datasheet http://www.datasheet4u.com/
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( hynix )
HYMP112P72CP8L-S6 register
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240pin DDR2 VLP Registerd DIMMs based on 1Gb C version - Hynix Semiconductor
