MC10141 반도체 회로 부품 판매점
Four Bit Universal Shift Register
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 Motorola Semiconductors |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Four Bit Universal Shift
Register
The MC10141 is a four–bit universal shift register which performs shift left, or
shift right, serial/parallel in, and serial/parallel out operations with no external
gating. Inputs S1 and S2 control the four possible operations of the register
without external gating of the clock. The flip–flops shift information on the
positive edge of the clock. The four operations are stop shift, shift left, shift right,
and parallel entry of data. The other six inputs are all data type inputs; four for
parallel entry data, and one for shifting in from the left (DL) and one for shifting
in from the right (DR).
PD = 425 mW typ/pkg (No Load)
fShift = 200 MHz typ
tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
S1 1 of 4
S2 Decoder
D3
Parallel Enter
Shift Right
DR
Shift Left
Hold
D2
D1 D0
DL
DQ DQ DQ DQ
C C CC
C
Q3 Q2 Q1 Q0
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
TRUTH TABLE
SELECT
OUTPUTS
S1 S2
LL
OPERATING MODE
Parallel Entry
Q0n+1 Q1n+1 Q2n+1
D0 D1 D2
LH
Shift Right*
Q1n Q2n
HL
Shift Left*
DL Q0n
HH
Stop Shift
Q0n Q1n
*Outputs as exist after pulse appears at “C” input with input conditions as
shown. (Pulse = Positive transition of clock input).
Q3n
Q1n
Q2n
Q3n+1
D3
DR
Q2n
Q3n
MC10141
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
DIP
PIN ASSIGNMENT
VCC1
Q2
Q3
C
DR
D3
S2
VEE
1
2
3
4
5
6
7
8
16 VCC2
15 Q1
14 Q0
13 DL
12 D0
11 D1
10 S1
9 D2
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
3–46
REV 5
MC10141
VIN
COAX
INPUT
PULSE GENERATOR
50–ohm termination to ground
located in each scope channel input.
SHIFT FREQUENCY TEST CIRCUIT
VCC1 = VCC2
+2.0 VDC
VOUT
25 uF
0.1 µF
Coax
All input and output cables to the
scope are equal lengths of 50–ohm
coaxial cable. Wire length should be
< 1/4 inch from TPin to input pin and
TPout to output pin.
1 16
DL
C Q0
D0
D1 Q1
D2
D3 Q2
S1
S2 Q3
DR
8
0.1 µF
TEST PROCEDURES:
1. SET D1, D2, D3 = +0.31 VDC (LOGIC L)
D0 = +1.11 VDC (LOGIC H)
2. APPY CLOCK PULSE
— VIH
VIL
TO SET Q0 HIGH.
3. MAINTAIN CLOCK LOW.
SET S1 = +0.31 VDC (LOGIC L)
S2 = +1.11 VDC (LOGIC H)
4. TEST SHIFT FREQUENCY
VEE = –3.2VDC
MECL Data
DL122 — Rev 6
3–47
MOTOROLA
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MC10141 register
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MC10141
Four Bit Universal Shift Register - ON Semiconductor
MC10141
Four Bit Universal Shift Register - Motorola Semiconductors