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DDR2 Registered DIMM Modules



Infineon Technologies AG 로고
Infineon Technologies AG
HYB18T256800AC 데이터시트, 핀배열, 회로
Data Sheet, V0.22,Feb. 2004
HYS72T32000GR (256 MByte)
HYS72T64001GR (512 MByte)
HYS72T64020GR (512 MByte)
DDR2 Registered DIMM Modules
Memory Products
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HYB18T256800AC 데이터시트, 핀배열, 회로
HYS72T32000GR, HYS72T64001GR
HYS72T64020GR
Preliminary Datasheet Rev. 0.22 (2.04)
Low Profile 240-pin Registered DDR2 SDRAM Modules Datasheet
256 MByte & 512 MByte Modules
PC2-3200R /-4200R /-5300R
• 240-pin Registered 8-Byte ECC Dual-In-Line
DDR2 SDRAM Module for PC, Workstation
and Server main memory applications
• One rank 32Mb x 72, 64Mb x 72 and
two ranks 64Mb × 72 organizations
• JEDEC standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAMs) with
+ 1.8 V (± 0.1 V) power supply
• Modules built with 256 Mb DDR2 SDRAMs in
60-ball FBGA chipsize packages
• Re-drive for all input signals using register
and PLL devices.
• OCD (Off-Chip Driver Impedance
Adjustment) and ODT (On-Die Termination)
• Serial Presence Detect with E2PROM
• Low Profile Modules form factor:
133.35 mm x 30,00 mm (MO-237)
• Based on JEDEC standard reference card
designs Raw Card “A”, “B” and “C”.
• Programmable CAS Latencies (3, 4 & 5),
Burst Length (4 & 8) and Burst Type.
• Auto Refresh and Self Refresh
• All inputs and outputs SSTL_1.8 compatible
• Performance:
Speed Grade Indicator
-5 -3.7 -3 Unit
Component Speed Grade on Module DDR2-400 DDR2-533 DDR2-667
Module Speed Grade
Max. Clock Frequency @ CL = 3
PC2-3200
200
PC2-4200
200
PC2-5300
200 MHz
Max. Clock Frequency@ CL = 4 & 5
200
266
333 MHz
1.0 Description
The INFINEON HYS72T32000GR, HYS72T64020GR and HYS72T64001 are low profile
Registered DIMM modules with 30,00 mm height based on DDR2 technology. DIMMs are available
in 32M x 72 (256 MByte), 2 x 32M x 72 (512 MByte) and 64M x 72 (512 MByte) organisation and
density, intended for mounting into 240 pin connector sockets.
The memory array is designed with 256Mbit Double Data Rate (DDR2) Synchronous DRAMs for
ECC applications. All control and address signals are re-driven on the DIMM using register devices
and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one
cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board, which provide
a proper voltage supply impedance over the whole frequency range of operations as number and
values are accordant to the JEDEC specification. The DIMMs feature serial presence detect based
on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to the customer.
INFINEON Technologies
2
2.04




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