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UM2681 반도체 회로 부품 판매점

Dual Asynchronous Receiver/Transmitter



UMC 로고
UMC
UM2681 데이터시트, 핀배열, 회로
(l)UMC
,===========Dual UM2681 SERIES
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Features
• Dual full-duplex asynchronous receiver/transmitter
• Ouadruple buffered receiver data registers
• Programmable data format
5 to 8 data bits plus parity
Odd, even, no parity or force parity
1, 1.5 or 2 stop bits programmable in 1/16 bit
increments'
• Programmable baud rate for each receiver and
transmiter' selectable from:
18 fixed rates: 50 to 38.4K baud
One user defined rate derived from programmable
timer/counter
External 1x or 16x clock
• Parity, framing, and overrun error detection
• False start bit detection
• Line break detection and generation
• Programmable channel mode
Normal (full duplex)
Automatic echo
Localloopback
Remote loopback
• Multi-function programmable 16-bit counter/timer
• Multi-function 7-bit input port
- Can serve as clock or control inputs
- Change of state detection on four inputs
• Multi-function 8-bit output port
Individual bit set/reset capability
- Outputs can be programmed to be status/interrupt
signals
• Versatile interrupt system
Single interrupt output with eight maskable inter-
rupting conditions
Output port can be configured to provide a total of
up to six separate wire-OR'able interrupt outputs
• Maximum data transfer: 1X-l MB/sec, 16X-125KB/sec
• Automatic wake-up mode for multidrop applications
• Start-end break interrupt/status
• Detects break which originates in the middle of a
character
• On-chip crystal oscillator
• TTL compatible
• Single +5V power supply
General Description
The UM2681 Dual Universal Asynchronous Receiver/
Transmitter (DUART) is a single chip NMOS-LSI com-
munications device that provides two independent full-
duplex asynchronous receiver/transmitter channels in a
single package. It interfaces directly with microprocessors
and may be used in a polled or interrupt driven system.
The operating mode and data format of each channel can
be programmed independently. Additionally, each receiver
and transmitter can select its operating speed as one of
eighteen fixed baud rates, a 16X clock derived from a
programmable counter/timer, or an external 1X or 16X
Pin Configuration
clock. The baud rate generator and counter/timer can
operate directly from a crystal or from external clock
inputs. The ability to independently program the operating
speed 'of the receiver and transmitter make the DUART
particularly attractive for dual-speed channel applications
such as clustered terminal systems.
Each receiver is quadruply buffered to minimize the
potential of receiver overrun or to reduce interrupt over-
head in interrupt driven systems. In addition, a flow
control capability is provided to disable a remote DUART
transmitter when the buffer of the receiving device is full.
OP2
OP4
OP6
DO
02
04
06
INTRN
AO
Al
A2
A3
WRN
RON
RXOB
TXOB
OPl
01
03
05
07
GNO
VCC
IP2
CEN
RESET
X2
Xl/CLK
RXOA
TXOA
OPO
DO
02
04
D6
INTRN
Al
A2
A3
WRN
RON
RXOB
TXOB
01
03
05
07
GNO
7-18
AO
Vcc
CEN
RESET
Kl/CLK
RXOA
TXOA
DO
02
04
06
INTRN


UM2681 데이터시트, 핀배열, 회로
(DUMC
Also provided on the UM2681 are a mUltipurpose 7-bit
input port and a multipurpose 8-bit output port. These
can be used as general purpose I/O ports or can be assigned
specific functions (such as clock inputs or status/interrupt
Absolute Maximum Ratings*
Operating ambient temperature .......... 0° to +70°C
Storage temperature .. . . . . . . . . . . .. _65° to +1500 C
All voltages with respect to ground .... -O.5V to +6.0V
UM2681 SERIES
outputs) under program control.
The UM2681 is available in three package versions to
satisfy various system requirements.
*Comments
Stress above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended period~ may affect device
reliability.
Block Diagram
I
Do·D7 _______BUS BUFFER __P=
RDN -
OPERATION CONTROL
I IWRN - _
ADDRESS
CEN
. DECODE
.
I IAO-A3--}--
RESET _
RIW CONTROL
A
INTRN-
INTERRUPT
CONTROL
IMR
ISR
.. v
t---
CHANNEL A
, TRANSMIT
HOLDING REG
TRANSMIT
SHIFT REGISTER
r------ TxDA
RECEIVE
HOLDING REG
(3)
RECEIVE
SHIFT REG
I rMRA 1,2
I CRA I
I SRA I
~RxDA
CHANNEL B
(AS ABOVE)
TxDB
RxDB
INPUT PORT
X1/CLK_
X2--
TIMING
I BAUD RATE
GENERATOR
I
I ICLOCK
SELECTORS
ICOUNTERfTlMER I
A
I XTALOSC I
CHANGE OF
i...J',,----./.
~~ 1--_ __.1
STATE
DETECTORS (4)
:II-~----'..IP_C_R_-I1
I--¥-- IPO-IP6
~ L-~.~A~C=R~='__j
OUTPUT PORT
FUNCTION
SELECT
LOGIC
~-T--- OPO-OP7
yy
I OPCR
. OPR
CSRA
CSRB
ACR
CTUR
CTLR
.---VCC
.---GND
7-19




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