|
Hynix Semiconductor |
Document Title
32K x8 bit 5.0V Low Power CMOS slow SRAM
Revision History
Revision No History
00 Revision History Insert
Revised
- Datasheet format change
- PDIP package type insert
- Pin configuration change
01 Revised
- tWP Value Change @55ns : 45ns -> 40ns
02 Marking Information Add
Revised
- AC Test Condition Add : 5pF Test Load
- tCLZ Value Change : 5ns - > 10ns
03 Changed Logo
- HYUNDAI -> hynix
GM76C256C Series
32Kx8bit CMOS SRAM
Draft Date
Jul.07.2000
Remark
Final
Nov.28.2000 Final
Dec.04.2000 Final
Apr.30.2001 Final
This document is a general product description and is subject to change without notice. Hynix
responsibility for use of circuits described. No patent licenses are implied.
Rev 03 / Apr. 2001
Electronics does not assume any
Hynix Semiconductor
GM76C256C Series
DESCRIPTION
The GM76C256C is a high-speed, low power and
32,786 X 8-bits CMOS Static Random Access
Memory fabricated using
Hynix's high
performance CMOS process technology. It is
suitable for use in low voltage operation and
battery back-up application. This device has a
data retention mode that guarantees data to
remain valid at the minimum power supply
voltage of 2.0 volt.
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Low power consumption
• Battery backup(L/LL-part)
- 2.0V(min.) data retention
• Standard pin configuration
- 28 pin 600mil PDIP
- 28 pin 330mil SOP
- 28 pin 8x13.4 mm TSOP-I
(Standard)
Product
Voltage Speed
No. (V) (ns)
GM76C256C
5.0 55/70/85
GM76C256CE 5.0
55/70/85
Note 1. Current value is max.
Operation
Current(mA)
10
10
Standby Current(uA)
L LL
40 20
60 30
Temperature
(°C)
0~70(Normal)
-25~85(Extended)
PIN CONNECTION
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
Vcc
/WE
A13
A8
A9
A11
/OE
A14
A12
A7
A6
A5
A4
A3
21 A10 A2
1
2
3
4
5
6
7
8
20 /CS A1 9
19
18
17
16
15
I/O8 A0
I/O7
I/O6
I/O5
I/O4
I/O1
I/O2
I/O3
Vss
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PDIP
SOP
Vcc
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
/OE
A11
A9
A8
A13
/WE
Vcc
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 A10
27 /CS
26 I/O8
25 I/O7
24 I/O6
23 I/O5
22 I/O4
21 Vss
20 I/O3
19 I/O2
18 I/O1
17 A0
16 A1
15 A2
TSOP-I(Standard)
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
A0 ~ A14
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select
Write Enable
Output Enable
Address Inputs
Data Input/Output
Power(+5.0V)
Ground
BLOCK DIAGRAM
A0 ROW DECODER
A14
/CS
/OE
/WE
MEMORY ARRAY
512x512
I/O1
I/O8
Rev 03 / Apr. 2000
2
|