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AMIC Technology |
LP61L1008A
Preliminary
128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
Features
n Single 3.3V ± 10% power supply
n Access times: 8/10/12 ns (max.)
n Current: Operating: 160/155/150mA (max.)
Standby: 5mA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL compatible
General Description
The LP61L1008A is a high speed 1,048,576-bit static
random access memory organized as 131,072 words by
8 bits and operates on a single 3.3V power supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configuration
n Center Power/Ground Pin Configuration
n Common I/O using three-state output
n Output enable and one chip enable inputs for easy
application
n Data retention voltage: 2.0V (min.)
n Available in 32-pin SOJ 300 mil package
The chip enable input is provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
A0
A1
A2
A3
CE
I/O1
I/O2
VCC
GND
I/O3
I/O4
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O8
26 I/O7
25 GND
24 VCC
23 I/O6
22 I/O5
21 A12
20 A11
19 A10
18 A9
17 A8
PRELIMINARY (August, 2001, Version 1.0)
1
AMIC Technology, Inc.
Block Diagram
A0
A14
A15
A16
I/O1
I/O8
LP61L1008A
DECODER
512 X 2048
MEMORY ARRAY
VCC
GND
INPUT
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
Pin Description
Pin No.
1 - 4, 13 - 21,
29- 32
12
28
5
6 –7, 10 - 11,
22 – 23, 26 - 27
8, 24
9, 25
Symbol
A0 - A16
WE
OE
CE
I/O1 - I/O8
VCC
GND
Description
Address Inputs
Write Enable
Output Enable
Chip Enable
Data Input/Outputs
Power Supply
Ground
PRELIMINARY (August, 2001, Version 1.0)
2
AMIC Technology, Inc.
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