WED2ZLRSP01S 반도체 회로 부품 판매점
Dual Array Synchronous Pipeline Burst NBL SRAM
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 White Electronic |
www.DataSheet4U.com
White Electronic Designs
WED2ZLRSP01S
512K x 32/256K x 32 Dual Array
Synchronous Pipeline Burst NBL SRAM
FEATURES
Fast clock speed: 166, 150, 133, and 100MHz
Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and
5.0ns
Single +2.5V ± 5% power supply (VCC)
Snooze Mode for reduced-standby power
Individual Byte Write control
Clock-controlled and registered addresses, data
I/Os and control signals
Burst control (interleaved or linear burst)
Packaging:
209-bump BGA package
Low capacitive bus loading
DESCRIPTION
The WED2ZLRSP01S, Dual Independent Array, NBL-
SSRAM device employs high-speed, Low-Power CMOS
silicon and is fabricated using an advanced CMOS process.
WEDC’s 24Mb, Sync Burst SRAM MCP integrates two
totally independent arrays, the first organized as a 512K x
32, and the second a 256K x 32.
All Synchronous inputs pass through registers controlled
by a positive edge triggered, single clock input per array.
The NBL or No Bus Latency Memory provides 100% bus
utilizaton, with no loss of cycles caused by change in modal
operation (Write to Read/Read to Write). All inputs except
for Asynchronous Output Enable and Burst Mode control
are synchronized on the positive or rising edge of Clock.
Burst order control must be tied either HIGH or LOW, Write
cycles are internally self-timed, and writes are initiated on
the rising edge of clock. This feature eliminates the need
for complex off-chip write pulse generation and proved
increased timing flexibility for incoming signals.
PIN CONFIGURATION
(TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11
A Vss A_DATb0 A_DATb1 A_DATb2 A_DATb3 Vss A_DATa0 A_DATa1 A_DATa2 A_DATa3
Vss
B NC A_DATb4 A_DATb5 A_DATb6 A_DATb7 Vss A_DATa4 A_DATa5 A_DATa6 A_DATa7
NC
C A_ADR A_ADR
A_OE# A_ADV A_BWEb Vss A_BWEa A_ZZ
A_ADR A_ADR A_ADR
D A_ADR
Vss
A_CKE#
Vcc
Vcc Vcc Vcc
Vcc
Vcc A_ADR A_ADR
E A_ADR A_CK A_GWE#
Vcc
Vcc Vcc Vcc
Vcc
Vcc A_ADR1 A_ADR0
F A_ADR
Vss
A_CS2#
Vcc
Vcc Vcc Vcc
Vcc
Vcc A_ADR A_ADR
G A_ADR A_ADR A_CS1# A_CS2 A_BWEc Vss A_BWEd A_LBO# A_ADR A_ADR A_ADR
H NC A_DATc0 A_DATc1 A_DATc2 A_DATc3 Vss A_DATd0 A_DATd1 A_DATd2 A_DATd3 NC
J Vss A_DATc4 A_DATc5 A_DATc6 A_DATc7 Vss A_DATd4 A_DATd5 A_DATd6 A_DATd7 Vss
K Vss
Vss
Vss
Vss
Vss Vss Vss
Vss
Vss Vss Vss
L Vss B_DATb0 B_DATb1 B_DATb2 B_DAT3 Vss B_DATa0 B_DATa1 B_DATa2 B_DATa3
Vss
M NC B_DATb4 B_DATb5 B_DATb6 B_DAT7 Vss B_DATa4 B_DATa5 B_DATa6 B_DATa7
NC
N B_ADR B_ADR
B_OE# B_ADV B_BWEb Vss B_BWEa B_ZZ
B_ADR B_ADR B_ADR
P B_ADR
Vss
B_CKE#
Vcc
Vcc Vcc Vcc
Vcc
Vcc B_ADR B_ADR
R B_ADR B_CK B_GWE#
Vcc
Vcc Vcc Vcc
Vcc
Vcc B_ADR1 B_ADR0
T B_ADR
Vss
B_CS2#
Vcc
Vcc Vcc Vcc
Vcc
Vcc B_ADR B_ADR
U B_ADR
NC
B_CS1# B_CS2 B_BWEc Vss B_BWEd B_LBO# B_ADR B_ADR B_ADR
V NC B_DATc4 B_DATc5 B_DATc6 B_DATc7 Vss B_DATd4 B_DATd5 B_DATd6 B_DATd7 NC
W Vss
B_DATc0 B_DATc1 B_DATc2 B_DATc3 Vss B_DATd0 B_DATd1 B_DATd2 B_DATd3
Vss
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2002
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
A_SA0-18
B_SA0-17
A_DQ0-31
B_DQ0-31
FIG. 1 BLOCK DIAGRAM
WED2ZLRSP01S
A_LBO#
A_ZZ
A_ADV
A_OE#
A_CKE#
A_WE#
A_CK
A_BWA#
A_BWB#
A_BWC#
A_BWD#
A_CS2#
A_CS2
A_CS1#
LBO#
ZZ
ADV
OE#
CKE#
WE#
CK
BWa#
BWb#
BWc#
BWd#
CS2#
CS2
CS1#
U1
DQ0-31
512K x 32
B_LBO#
B_ZZ
B_ADV
B_OE#
B_CKE#
B_WE#
B_CK
B_BWA#
B_BWB#
B_BWC#
B_BWD#
B_CS2#
B_CS2
B_CS1#
LBO#
ZZ
ADV
OE#
CKE#
WE#
CK
BWa#
BWb#
BWc#
BWd#
CS2#
CS2
CS1#
U2
DQ0-31
256K x 32
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2002
Rev. 0
2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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WED2ZLRSP01S ram
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