IDT71V2546SA133PF 반도체 회로 부품 판매점
128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
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 Integrated Device Technology |
128K x 36, 256K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
IDT71V2546S
IDT71V2548S
IDT71V2546SA
IDT71V2548SA
Features
x 128K x 36, 256K x 18 memory configurations
x Supports high performance system speed - 150 MHz
(3.8 ns Clock-to-Data Access)
x ZBTTM Feature - No dead cycles between write and read
cycles
x Internally synchronized output buffer enable eliminates the
need to control OE
x Single R/W (READ/WRITE) control pin
x Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x 4-word burst capability (interleaved or linear)
x Individual byte write (BW1 - BW4) control (May tie active)
x Three chip enables for simple depth expansion
x 3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
x Optional Boundary Scan JTAG Interface (IEEE1149.1
complaint)
x Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array
Description
The IDT71V2546/48 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBTTM, or Zero Bus
Turnaround.
Pin Description Summary
A 0-A 17
Address Inputs
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2546/48 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V2546/48 to
be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2546/48 has an on-chip burst counter. In the burst mode,
the IDT71V2546/48 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. TheLBO pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2546/48 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
Input Synchronous
CE1, CE2, CE2
Chip Enables
Input Synchronous
OE Output Enable
Input Asynchronous
R/W Read/Write Signal
Input Synchronous
CEN Clock Enable
Input Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input Synchronous
CLK Clock
Input N/A
ADV/LD
Adv ance burst address / Load new address
Input Synchronous
LBO Linear / Interleaved Burst Order
Input Static
TMS Test Mode Select
Input Synchronous
TDI Test Data Input
Input Synchronous
TCK Test Clock
Input N/A
TDO Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input Asynchronous
ZZ Sleep Mode
Input Synchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
Static
VSS Ground
Supply
Static
©2004 Integrated Device Technology, Inc.
1
5294 tbl 01
SEPTEMBER 2004
DSC-5294/04
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O Active
Description
A0-A17
Address Inputs
I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it
is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip
deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter
is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled
high.
R/W
Read / Write
I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
CEN
Clock Enable
I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock
are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the
low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of
clock.
BW1-BW4
Individual Byte
Write Enables
I LOW Synchronous byte write enables. Each 9-bit b yte has its own active low byte write enable. On load write cycles
(When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is
sampled high. The appro priate byte(s) of data are written into the de vice two cycles later. BW1-BW4 can all be
tied low if always doing write to the entire 36-bit word.
CE1, CE2
Chip Enables
I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V2546/48. (CE1 or
CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.
The ZBTTM has a two cycle de select, i.e., the data bus will tri-state two clo ck cycles after deselect is initiated.
CE2
Chip Enable
I HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted
polarity but otherwise identical to CE1 and CE2.
CLK
Clock
I N/A This is the clock input to the IDT71V2546/48. Except for OE, all timing references for the device are made with
respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
OE
Output Enable
I LOW Asynchronous output enable. OE must be low to read data from the 71V2546/48. When OE is high the I/O pins
are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
TMS
Test Mode Select
I
N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI
Test Data Input
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK
Test Clock
I
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured o n rising edge of TCK,
while test outputs are d riven from the falling edge of TCK. This pin has an internal pullup.
TDO
Test Data Output
O
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
TRST
JTAG Reset
(Optional)
Optional Asynchronous JTAG reset. Can be used to reset the TAP co ntroller, but not required. JTAG reset
I LOW occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup.
Synchronous sleep mode inp ut. ZZ HIGH will gate the CLK internally and power down the IDT71V2546/2548 to
ZZ
Sleep Mode
I HIGH its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
VDD
Power Supply
N/A N/A 3.3V core power supply.
VDDQ
Power Supply
N/A N/A 2.5V I/O Supply.
VSS
Ground
N/A N/A Ground.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
5294 tbl 02
6.422
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IDT71V2546SA133PF ram
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IDT71V2546SA133PF
128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs - Integrated Device Technology
IDT71V2546SA133PFI
128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs - Integrated Device Technology