|
Hitachi Semiconductor |
HM628128D Series
1 M SRAM (128-kword × 8-bit)
ADE-203-996 (Z)
Preliminary, Rev. 0.0
Jan. 20, 1999
Description
The Hitachi HM628128D Series is 1-Mbit static RAM organized 131,072-kword × 8-bit. HM628128D
Series has realized higher density, higher performance and low power consumption by employing Hi-
CMOS process technology. The HM628128D Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It has package variations of standard 32-pin plastic DIP,
standard 32-pin plastic SOP and standard 32-pin plastic TSOPI.
Features
• Single 5 V supply: 5 V ± 10%
• Access time: 55 ns/70 ns (max)
• Power dissipation
Active: 30 mW/MHz (typ)
Standby: 10 µW (typ)
• Completely static memory.
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible all inputs
• Battery backup operation
2 chip selection for battery backup
HM628128D Series
Ordering Information
Type No.
HM628128DLP-5
HM628128DLP-7
HM628128DLP-5SL
HM628128DLP-7SL
HM628128DLP-5UL
HM628128DLP-7UL
HM628128DLFP-5
HM628128DLFP-7
HM628128DLFP-5SL
HM628128DLFP-7SL
HM628128DLFP-5UL
HM628128DLFP-7UL
HM628128DLTS-5
HM628128DLTS-7
HM628128DLTS-5SL
HM628128DLTS-7SL
HM628128DLTS-5UL
HM628128DLTS-7UL
HM628128DLT-5
HM628128DLT-7
HM628128DLT-5SL
HM628128DLT-7SL
HM628128DLT-5UL
HM628128DLT-7UL
HM628128DLR-5
HM628128DLR-7
HM628128DLR-5SL
HM628128DLR-7SL
HM628128DLR-5UL
HM628128DLR-7UL
Access time
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
Package
600-mil 32-pin plastic DIP (DP-32)
525-mil 32-pin plastic SOP (FP-32D)
8 × 13.4 mm 32-pin plastic TSOP I (TFP-32DC)
Normal-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32D)
Reverse-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32DR)
2
|