CY7C1562XV18 판매점 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture

CY7C1562XV18/CY7C1564XV18

72-Mbit QDR® II+ Xtreme SRAM Two-Word

Burst Architecture (2.5 Cycle Read Latency)

72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 450 MHz clock for high bandwidth

■ Two-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 900 MHz) at 450 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR™-II+ Xtreme operates with 2.5 cycle read latency when

DOFF is asserted HIGH

■ Operates similar to QDR-I device with 1 cycle read latency

when DOFF is asserted LOW

■ Available in × 18, and × 36 configurations

■ Full data coherency, providing most current data

■ Core VDD = 1.8 V± 0.1 V; I/Os VDDQ = 1.4 V to 1.6 V

❐ Supports 1.5 V I/O supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase-Locked Loop (PLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.5 cycles:

CY7C1562XV18 – 4M × 18

CY7C1564XV18 – 2M × 36

Functional Description

The CY7C1562XV18, and CY7C1564XV18 are 1.8 V

Synchronous Pipelined SRAMs, equipped with QDR® II+

architecture. Similar to QDR II architecture, QDR II+ architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has dedicated data

outputs to support read operations and the write port has

dedicated data inputs to support write operations. QDR II+

architecture has separate data inputs and data outputs to

completely eliminate the need to “turnaround” the data bus that

exists with common I/Os devices. Access to each port is through

a common address bus. Addresses for read and write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR II+ Xtreme read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with two 18-bit

words (CY7C1562XV18), or 36-bit words (CY7C1564XV18) that

burst sequentially into or out of the device. Because data can be

transferred into and out of the device on every rising edge of both

input clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus “turnarounds”.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

For a complete list of related documentation, click here.

Selection Guide

Maximum Operating Frequency

Maximum Operating Current

Description

450 MHz 366 MHz Unit

450 366 MHz

× 18 1205

970 mA

× 36 1445

1165

Cypress Semiconductor Corporation • 198 Champion Court

Document Number: 001-68998 Rev. *F

• San Jose, CA 95134-1709 • 408-943-2600

Revised July 7, 2016

CY7C1562XV18 반도체 회로 부품 판매점

72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture

국내 전력반도체 판매점

일반적인 전자부품 판매점

관련 데이터시트