IS61DDPB22M18B1 판매점 - 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM

IS61DDPB22M18B1 반도체 회로 부품 판매점

36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM

Integrated Silicon Solution

IS61DDPB22M18B/B1/B2

IS61DDPB21M36B/B1/B2

2Mx18, 1Mx36

36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM

(2.5 Cycle Read Latency)

SEPTEMBER 2014

FEATURES

DESCRIPTION

 1Mx36 and 2Mx18 configuration available.

 On-chip Delay-Locked Loop (DLL) for wide data

valid window.

 Common I/O read and write ports.

 Synchronous pipeline read with self-timed late write

operation.

 Double Data Rate (DDR) interface for read and

write input ports.

 2.5 cycle read latency.

 Fixed 2-bit burst for read and write operations.

 Clock stop support.

 Two input clocks (K and K#) for address and control

registering at rising edges only.

 Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.

 +1.8V core power supply and 1.5, 1.8V VDDQ, used

with 0.75, 0.9V VREF.

 HSTL input and output interface.

 Registered addresses, write and read controls, byte

writes, data in, and data outputs.

 Full data coherency.

 Boundary scan using limited set of JTAG 1149.1

functions.

 Byte write capability.

 Fine ball grid array (FBGA) package:

13mm x 15mm & 15mm x 17mm body size

165-ball (11 x 15) array

 Programmable impedance output drivers via 5x

user-supplied precision resistor.

 Data Valid Pin (QVLD).

 ODT (On Die Termination) feature is supported

optionally on data input, K/K#, and BWx#.

 The end of top mark (B/B1/B2) is to define options.

IS61DDPB21M36B : Don’t care ODT function and

pin connection

IS61DDPB21M36B1 : Option1

IS61DDPB21M36B2 : Option 2

Refer to more detail description at page 6 for each

ODT option.

The 36Mb IS61DDPB21M36B/B1/B2 and

IS61DDPB22M18B/B1/B2 are synchronous, high-

performance CMOS static random access memory (SRAM)

devices. These SRAMs have a common I/O bus. The rising

edge of K clock initiates the read/write operation, and all

internal operations are self-timed. Refer to the Timing

Reference Diagram for Truth Table for a description of the

basic operations of these DDR-IIP (Burst of 2) CIO SRAMs.

Read and write addresses are registered on alternating rising

edges of the K clock. Reads and writes are performed in

double data rate.

The following are registered internally on the rising edge of

the K clock:

 Read/write address

 Read enable

 Write enable

 Byte writes

 Data-in for first burst addresses

 Data-Out for second burst addresses

The following are registered on the rising edge of the K#

clock:

 Byte writes

 Data-in for second burst addresses

 Data-Out for first burst addresses

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after

the write address. The first data-in burst is clocked one cycle

later than the write command signal, and the second burst is

timed to the following rising edge of the K# clock.

During the burst read operation, the data-outs from the first

bursts are updated from output registers of the third rising

edge of the K# clock (starting two and half cycles later after

read command). The data-outs from the second burst are

updated with the fourth rising edge of the K clock where read

command receives at the first rising edge of K.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

9/10/2014

IS61DDPB22M18B/B1/B2

IS61DDPB21M36B/B1/B2

Package ballout and description

x36 FBGA Ball Configuration (Top View)

1234

CQ# NC/SA1 SA

R/W#

B NC DQ27 DQ18 SA

C NC NC DQ28 VSS

D NC DQ29 DQ19 VSS

DQ20

VDDQ

F NC DQ30 DQ21 VDDQ

G NC DQ31 DQ22 VDDQ

Doff#

VREF

VDDQ

DQ32

VDDQ

DQ23

VDDQ

L NC DQ33 DQ24 VDDQ

M NC NC DQ34 VSS

N NC DQ35 DQ25 VSS

P NC NC DQ26 SA

TDO

TCK

BW2#

BW3#

VSS

VDD

VSS

QVLD

ODT

BW1#

BW0#

VSS

VDD

VSS

LD#

VSS

VDDQ

VSS

Notes:

1. The following balls are reserved for higher densities: 10A for 72Mb, and 2A for 144Mb.

VDDQ

NC/SA1

DQ17

DQ15

VREF

DQ13

DQ12

DQ11

DQ9

TMS

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

x18 FBGA Ball Configuration (Top View)

1234

CQ# NC/SA1 SA

R/W#

NC DQ9 NC

C NC NC NC VSS

D NC NC DQ10 VSS

DQ11

VDDQ

NC DQ12 NC

VDDQ

DQ13

VDDQ

Doff#

VREF

VDDQ

J NC NC NC VDDQ

DQ14

VDDQ

NC DQ15 NC

VDDQ

M NC NC NC VSS

N NC NC DQ16 VSS

P NC NC DQ17 SA

TDO

TCK

BW1#

NC/SA1

VSS

VDD

VSS

QVLD

ODT

NC/SA1

BW0#

VSS

VDD

VSS

LD#

VSS

VDDQ

VSS

VDDQ

Notes:

1. The following balls are reserved for higher densities: 2A for 72Mb, 7A for 144Mb, and 5B for 288Mb.

DQ7

VREF

DQ4

DQ1

TMS

DQ8

DQ6

DQ5

DQ3

DQ2

DQ0

TDI

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

9/10/2014

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IS61DDPB22M18B1 ram

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IS61DDPB22M18B1 반도체 회로 부품 판매점

36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM

국내 전력반도체 판매점

일반적인 전자부품 판매점

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