CD4060BMS 반도체 회로 부품 판매점
CMOS 14 Stage Ripple-Carry Binary Counter/Divider and Oscillator
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 Intersil Corporation |
CD4060BMS
December 1992
CMOS 14 Stage Ripple-Carry
Binary Counter/Divider and Oscillator
Features
Pinout
• High Voltage Type (20V Rating)
• Common Reset
• 12MHz Clock Rate at 15V
• Fully Static Operation
• Buffered Inputs and Outputs
• Schmitt Trigger Input Pulse Line
• Standardized, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
Q12 1
Q13 2
Q14 3
Q6 4
Q5 5
Q7 6
Q4 7
VSS 8
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of Functional Diagram
‘B’ Series CMOS Devices”
16 VDD
15 Q10
14 Q8
13 Q9
12 RESET
11 øI
10 ø0
9 ø0
Oscillator Features
• All Active Components on Chip
• RC or Crystal Oscillator Configuration
• RC Oscillator Frequency of 690kHz Min. at 15V
Applications
• Control counters
• Timers
• Frequency Dividers
• Time Delay Circuits
Description
CD4060BMS consists of an oscillator section and 14 ripple
carry binary counter stages. The oscillator configuration allows
design of either RC or crystal oscillator circuits. A RESET input
is provided which resets the counter to the all O’s state and dis-
ables the oscillator. A high level on the RESET line accom-
plishes the reset function. All counter stages are master slave
flip-flops. The state of the counter is advanced one step in
binary order on the negative transition of øI (and ø0). All inputs
and outputs are fully buffered. Schmitt trigger action on the
input pulse line permits unlimited input pulse rise and fall times.
The CD4060BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP H4W
Frit Seal DIP
H1F
Ceramic Flatpack H6W
R 12
øI 11
VSS = 8
VDD = 16
ø0 9
ø0 10
14 STAGE
RIPPLE
COUNTER
AND
OSCILLATOR
Q4
7
Q5
5
Q6
4
Q7
6
Q8
14
Q9 13
Q10
15
Q12
1
Q13
2
Q14
3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-949
File Number 3317
Specifications CD4060BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
(Excluding pins 9 & 10)
IOL5 VDD = 5V, VOUT = 0.4V
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
0.53 - mA
1
+25oC
1.4 - mA
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
(Excluding pins 9 & 10) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -0.53 mA
1
+25oC
- -1.8 mA
IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
7
7
+25oC
+25oC
VOH > VOL < V
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
(Note 2)
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
Input Voltage High
(Note 2)
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
Input Voltage Low
(Note 2)
VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC -
4V
Input Voltage High
(Note 2)
VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-950
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CD4060BMS oscillator
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