MTD20N03HDL 반도체 회로 부품 판매점
Power MOSFET ( Transistor )
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 ON Semiconductor |
MTD20N03HDL
Preferred Device
Power MOSFET
20 Amps, 30 Volts, Logic Level
N−Channel DPAK
This advanced Power MOSFET is designed to withstand high
energy in the avalanche and commutation modes. This energy efficient
design also offers a drain−to−source diode with a fast recovery time.
Designed for low voltage, high speed switching applications in power
supplies, converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
Features
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Pb−Free Packages are Available
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value
Drain−Source Voltage
VDSS
30
Drain−Gate Voltage (RGS = 1.0 MW)
VDGR
30
Gate−Source Voltage
− Continuous
− Non−Repetitive (tp ≤ 10 ms)
VGS
VGSM
±15
± 20
Drain Current − Continuous
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (tp ≤ 10 ms)
ID 20
ID 16
IDM 60
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C (Note 2)
PD
74
0.6
1.75
Operating and Storage Temperature Range
TJ, Tstg − 55 to
150
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
W
W/°C
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak
IL = 20 Apk, L = 1.0 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
EAS 200 mJ
RqJC
RqJA
RqJA
TL
°C/W
1.67
100
71.4
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR−4 board using the minimum recommended
pad size.
2. When surface mounted to an FR−4 board using the 0.5 sq.in. drain pad size.
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V(BR)DSS
30 V
RDS(on) TYP
30 mW@5.0 V
ID MAX
20 A
(Note 1)
N−Channel
D
G
S
MARKING DIAGRAM & PIN ASSIGNMENTS
4
12
3
DPAK
CASE 369C
STYLE 2
1 Gate
2 Drain
3 Source
YWW
20N
03HLG
4
Drain
4
1 Gate
1
2
3
DPAK
CASE 369D
STYLE 2
2
Drain
3 Source
YWW
20N
03HL
4
Drain
Y = Year
WW = Work Week
20N03HL = Device Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
MTD20N03HDL/D
MTD20N03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0) (Note 5)
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate−Body Leakage Current
(VGS = ±15 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
(Cpk ≥ 2.0) (Note 5)
Static Drain−to−Source On−Resistance
(VGS = 4.0 Vdc, ID = 10 Adc)
(VGS = 5.0 Vdc, ID = 10 Adc)
Drain−to−Source On−Voltage (VGS = 5.0 Vdc)
(ID = 20 Adc)
(ID = 10 Adc, TJ = 125°C)
Forward Transconductance
(VDS = 5.0 Vdc, ID = 10 Adc)
(Cpk ≥ 2.0) (Note 5)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 15 Vdc, ID = 20 Adc,
VGS = 5.0 Vdc, RG = 9.1 W)
Fall Time
Gate Charge (See Figure 8)
(VDS = 24 Vdc, ID = 20 Adc, VGS = 5.0 Vdc)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(Cpk ≥ 2.0) (Note 5)
(IS = 20 Adc, VGS = 0 Vdc)
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(See Figure 15)
(IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms)
Reverse Recovery Stored
Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
5. Reflects typical values. Cpk = Absolute Value of Spec (Spec−AVG/3.516 mA).
Symbol
V(BR)DSS
IDSS
IGSS
VGS(th)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
trr
ta
tb
QRR
LD
LS
Min Typ Max Unit
30 −
− 43
Vdc
−
− mV/°C
mAdc
− − 10
− − 100
nAdc
− − 100
Vdc
1.0 1.5 2.0
− 5.0 − mV/°C
W
− 0.034 0.040
0.030 0.035
Vdc
− 0.55 0.8
− − 0.7
10 13
mhos
−
−
880 1260
pF
− 300 420
− 80 150
− 13 20 ns
− 212 238
− 23 40
− 84 140
−
13.4 18.9
nC
− 3.0 −
− 7.3 −
− 6.0 −
Vdc
− 0.95 1.1
− 0.87 −
− 33 − ns
− 23 −
− 10 −
− 33 − mC
nH
− 4.5 −
nH
− 7.5 −
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