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SIZ300DT 반도체 회로 부품 판매점

Dual N-Channel 30 V (D-S) MOSFETs



Vishay Siliconix 로고
Vishay Siliconix
SIZ300DT 데이터시트, 핀배열, 회로
www.DataSheet.co.kr
SiZ300DT
Vishay Siliconix
Dual N-Channel 30 V (D-S) MOSFETs
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
0.0240 at VGS = 10 V
Channel-1 30
0.0320 at VGS = 4.5 V
0.0110 at VGS = 10 V
Channel-2 30
0.0165 at VGS = 4.5 V
ID (A)a Qg (Typ.)
11
3.5 nC
11
28
21.2 nC
28
PowerPAIR® 3 x 3
Pin 1
S1/D2
8
G2 7
S2 6
S2 5
S2
G1
D1
3 mm
1 D1
2
D1 3
D1
4
3 mm
Ordering Information:
SiZ300DT-T1-GE3 (Lead (Pb)-free and Halogen-free)
FEATURES
Halogen-free According to IEC 61249-2-21
Definition
• PowerPAIR Optimizes High-Side and Low-Side
MOSFETs for Synchronous Buck Converters
• TrenchFET® Power Mosfets
• 100 % Rg and UIS Tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Computing System Power
• POL
• Synchronous Buck Converter
D1
G1
N-Channel 1
MOSFET
S1/D2
G2
N-Channel 2
MOSFET
S2
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Channel-1
Channel-2
Unit
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Pulsed Drain Current (t = 300 µs)
Continuous Source Drain Diode Current
Avalanche Current
Single Pulse Avalanche Energy
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
TA = 25 °C
TA = 25 °C
L = 0.1 mH
VDS
VGS
ID
IDM
IS
IAS
EAS
11a
11a
9.8b, c
7.8b, c
30
11a
3.2b, c
12
7
30
± 20
28a
28a
14.9b, c
11.9b, c
40
26
3.8b, c
15
11
V
A
mJ
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)d, e
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
PD
TJ, Tstg
16.7 31
10.7 20
3.7b, c
4.2b, c
2.4b, c
2.7b, c
- 55 to 150
260
W
°C
Notes:
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See solder profile (www.vishay.com/ppg?73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not
plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required
to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 67715
www.vishay.com
S11-1646-Rev. B, 15-Aug-11
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Datasheet pdf - http://www.DataSheet4U.net/


SIZ300DT 데이터시트, 핀배열, 회로
www.DataSheet.co.kr
SiZ300DT
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Channel-1
Parameter
Symbol
Typ.
Maximum Junction-to-Ambienta, b
Maximum Junction-to-Case (Drain)
t 10 s
Steady State
RthJA
RthJC
27
6
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. Maximum under steady state conditions is 69 °C/W for channel-1 and 64 °C/W for channel-2.
Max.
34
7.5
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
Gate Threshold Voltage
VDS
VDS/TJ
VGS(th)/TJ
VGS(th)
VGS = 0, ID = 250 µA
VGS = 0 V, ID = 250 µA
ID = 250 µA
ID = 250 µA
ID = 250 µA
ID = 250 µA
VDS = VGS, ID = 250 µA
VDS = VGS, ID = 250 µA
Gate Source Leakage
IGSS
VDS = 0 V, VGS = ± 20 V
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward Transconductanceb
Dynamica
IDSS
ID(on)
RDS(on)
gfs
VDS = 30 V, VGS = 0 V
VDS = 30 V, VGS = 0 V
VDS = 30 V, VGS = 0 V, TJ = 55 °C
VDS = 30 V, VGS = 0 V, TJ = 55 °C
VDS 5 V, VGS = 10 V
VDS 5 V, VGS = 10 V
VGS = 10 V, ID = 9.8 A
VGS = 10 V, ID = 15 A
VGS = 4.5 V, ID = 8.5 A
VGS = 4.5 V, ID = 12 A
VDS = 15 V, ID = 9.8 A
VDS = 15 V, ID = 15 A
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Ciss
Coss
Crss
Channel-1
VDS = 15 V, VGS = 0 V, f = 1 MHz
Channel-2
VDS = 15 V, VGS = 0 V, f = 1 MHz
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDS = 15 V, VGS = 10 V, ID = 9.8 A
Qg VDS = 15 V, VGS = 10 V, ID = 15 A
Channel-1
VDS = 15 V, VGS = 4.5 V, ID = 9.8 A
Qgs
Channel-2
Qgd VDS = 15 V, VGS = 4.5 V, ID = 15 A
Gate Resistance
Rg
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width 300 µs, duty cycle 2 %.
f = 1 MHz
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Channel-2
Typ. Max.
24 30
3.2 4
Unit
°C/W
Min. Typ. Max. Unit
30
V
30
24
30
- 4.1
mV/°C
-5
1 2.4
V
1 2.2
± 100
± 100
nA
1
1
µA
5
5
10
A
10
0.0200 0.0240
0.0090 0.0110
0.0265 0.0320
0.0135 0.0165
30
S
30
400
730
125
155
25
65
7.4 12
14.2 22
3.5 5.3
6.8 11
1.5
2.2
1.1
2.3
0.5 2.6 5.2
0.5 2.6 5.2
pF
nC
www.vishay.com
Document Number: 67715
2 S11-1646-Rev. B, 15-Aug-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Datasheet pdf - http://www.DataSheet4U.net/




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