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SPP1413
P-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPP1413 is the P-Channel logic enhancement mode
power field effect transistors are produced using high cell
density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery powered
circuits where high-side switching , and low in-line
power loss are needed in a very small outline surface
mount package.
APPLICATIONS
z Power Management in Note book
z Portable Equipment
z Battery Powered System
z DC/DC Converter
z Load Switch
z DSC
z LCD Display inverter
FEATURES
-20V/-2.4A,RDS(ON)=130mΩ@VGS=- 10V
-20V/-2.9A,RDS(ON)=150mΩ@VGS=- 4.5V
Super high density cell design for extremely low
RDS (ON)
Exceptional on-resistance and maximum DC
current capability
SOT-323 ( SC–70 ) package design
PIN CONFIGURATION ( SOT-323 ; SC-70 )
PART MARKING
2006/03/20 Ver.2
Page 1
SPP1413
P-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
Symbol
G
S
D
Description
Gate
Source
Drain
ORDERING INFORMATION
Part Number
SPP1413S32RG
※ Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
※ SPP1413S32RG : Tape Reel ; Pb – Free
Package
SOT-323
Part Marking
13YW
ABSOULTE MAXIMUM RATINGS
(TA=25℃ Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(TJ=150℃)
Pulsed Drain Current
TA=25℃
TA=70℃
Continuous Source Current(Diode Conduction)
Power Dissipation
Operating Junction Temperature
TA=25℃
TA=70℃
Storage Temperature Range
Thermal Resistance-Junction to Ambient
Symbol
VDSS
VGSS
ID
IDM
IS
PD
TJ
TSTG
RθJA
Typical
-20
±12
-2.9
-2.0
-8
-1.4
0.33
0.21
-55/150
-55/150
105
Unit
V
V
A
A
A
W
℃
℃
℃/W
2006/03/20 Ver.2
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