ALD1105 반도체 회로 부품 판매점
DUAL N-CHANNEL AND DUAL P-CHANNEL MATCHED MOSFET PAIR
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 Advanced Linear Devices |
ADVANCED
LINEAR
DEVICES, INC.
DUAL N-CHANNEL AND DUAL P-CHANNEL MATCHED MOSFET PAIR
ALD1105
GENERAL DESCRIPTION
The ALD1105 is a monolithic dual N-channel and dual P-channel
complementary matched transistor pair intended for a broad range of
analog applications. These enhancement-mode transistors are
manufactured with Advanced Linear Devices' enhanced ACMOS silicon
gate CMOS process. It consists of an ALD1116 N-channel MOSFET pair
and an ALD1117 P-channel MOSFET pair in one package. The ALD1105
is a low drain current, low leakage current version of the ALD1103.
The ALD1105 offers high input impedance and negative current temperature
coefficient. The transistor pair is matched for minimum offset voltage and
differential thermal response, and it is designed for precision signal
switching and amplifying applications in +2V to +12V systems where low
input bias current, low input capacitance and fast switching speed are
desired. Since these are MOSFET devices, they feature very large (almost
infinite) current gain in a low frequency, or near DC, operating environment.
When used in complementary pairs, a dual CMOS analog switch can be
constructed. In addition, the ALD1105 is intended as a building block for
differential amplifier input stages, transmission gates, and multiplexer
applications.
The ALD1105 is suitable for use in precision applications which require
very high current gain, beta, such as current mirrors and current sources.
The high input impedance and the high DC current gain of the Field Effect
Transistors result in extremely low current loss through the control gate.
The DC current gain is limited by the gate input leakage current, which is
specified at 30pA at room temperature. For example, DC beta of the device
at a drain current of 3mA at 25°C is = 3mA/30pA = 100,000,000.
FEATURES
• Thermal tracking between N-channel and P-channel pairs
• Low threshold voltage of 0.7V for both N-channel &
P-channel MOSFETS
• Low input capacitance
• Low Vos -- 10mV
• High input impedance -- 1013Ω typical
• Low input and output leakage currents
• Negative current (IDS) temperature coefficient
• Enhancement mode (normally off)
• DC current gain 109
• Matched N-channel and matched P-channel in one package
• RoHS compliant
APPLICATIONS
• Precision current mirrors
• Complementary push-pull linear drives
• Analog switches
• Choppers
• Differential amplifier input stage
• Voltage comparator
• Data converters
• Sample and Hold
• Analog inverter
• Precision matched current sources
PIN CONFIGURATION
DN1 1
GN1 2
14 DN2
13 GN2
SN1 3
V- 4
12 SN2
11 V+
DP1 5
10 DP2
GP1 6
9 GP2
SP1
78
TOP VIEW
SBL, PBL, DB PACKAGES
SP2
BLOCK DIAGRAM
N GATE 1 (2)
N DRAIN 1 (1)
N DRAIN 2 (14)
N SOURCE 1 (3)
SUBSTRATE (4)
N SOURCE 2 (12)
N GATE 2 (13)
ORDERING INFORMATION (“L” suffix denotes lead-free (RoHS))
Operating Temperature Range*
0°C to +70°C
0°C to +70°C
-55°C to +125°C
14-Pin
Small Outline
Package (SOIC)
14-Pin
Plastic Dip
Package
14-Pin
CERDIP
Package
ALD1105SBL
ALD1105PBL
ALD1105DB
* Contact factory for leaded (non-RoHS) or high temperature versions.
P GATE 1 (6)
P DRAIN 1 (5)
P DRAIN 2 (10)
P SOURCE 1 (7)
SUBSTRATE (11)
P SOURCE 2 (8)
P GATE 2 (9)
Rev 2.0 ©2012 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, CA 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286
www.aldinc.com
ABSOLUTE MAXIMUM RATINGS
Drain-source voltage, VDS
Gate-source voltage, VGS
Power dissipation
Operating temperature range SBL, PBL packages
DB package
Storage temperature range
Lead temperature, 10 seconds
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
10.6V
10.6V
500mW
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
+260°C
OPERATING ELECTRICAL CHARACTERISTICS
TA = 25°C unless otherwise specified
N - Channel
Parameter Symbol Min Typ Max
Gate Threshold VT
Voltage
0.4 0.7 1.0
Unit
V
Test
Conditions
IDS = 1µA VGS = VDS
Offset Voltage VOS
VGS1 - VGS2
2 10 mV IDS = 10µA VGS = VDS
Gate Threshold
Temperature TCVT -1.2 mV/°C
Drift
On Drain
Current
IDS (ON) 3 4.8
mA VGS = VDS = 5V
Trans-.
conductance
Gfs
1 1.8
mmho VDS = 5V IDS= 10mA
Mismatch
Output
Conductance
∆Gfs
GOS
0.5 %
200 µmho VDS = 5V IDS = 10mA
Drain Source RDS(ON)
ON Resistance
350 500 Ω
VDS = 0.1V VGS = 5V
Drain Source
ON Resistance ∆RDS(ON)
Mismatch
0.5
% VDS = 0.1V VGS = 5V
Drain Source
Breakdown
Voltage
BVDSS 12
V IDS = 1µA VGS =0V
Off Drain
Current
IDS(OFF)
Gate Leakage IGSS
Current
Input
Capacitance
CISS
10 400 pA
4 nA
0.1 30 pA
1 nA
1 3 pF
VDS =12V IGS = 0V
TA = 125°C
VDS = 0V VGS =12V
TA = 125°C
P - Channel
Min Typ Max
-0.4 -0.7 -1.0
Unit
V
Test
Conditions
IDS = -1µA VGS = VDS
2 10 mV
IDS = -10µA VGS = VDS
-1.3 mV/°C
-1.3 -2
mA VGS = VDS = -5V
0.25 0.67
mmho VDS = -5V IDS= -10mA
0.5 %
40 µmho VDS = -5V IDS = -10mA
1200 1800 Ω
VDS = -0.1V VGS = -5V
0.5 % VDS = -0.1V VGS = -5V
-12 V
10 400 pA
4 nA
1 30 pA
1 nA
1 3 pF
IDS = -1µA VGS =0V
VDS = -12V VGS = 0V
TA = 125°C
VDS = 0V VGS =-12V
TA = 125°C
ALD1105
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ALD1105 mosfet
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