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SIS902DN 반도체 회로 부품 판매점

Dual N-Channel 75-V (D-S) MOSFET



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Vishay
SIS902DN 데이터시트, 핀배열, 회로
Dual N-Channel 75-V (D-S) MOSFET
SiS902DN
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω)
0.186 at VGS = 10 V
75
0.228 at VGS = 4.5 V
ID (A)
4e
4e
Qg (Typ.)
2.1 nC
PowerPAK 1212-8
3.30 mm
D1
8
D1
7
D2
6 D2
5
S1
1
G1
2
3.30 mm
S2
3 G2
4
Bottom View
Ordering Information: SiS902DN-T1-GE3 (Lead (Pb)-free and Halogen-free)
FEATURES
Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• Low Thermal Resistance PowerPAK®
Package with Small Size and Low 1.07 mm
Profile
• 100 % Rg Tested
• 100 % UIS Tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• POL
D1
D2
G1 G2
S1
N-Channel MOSFET
S2
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
Limit
Unit
Drain-Source Voltage
Gate-Source Voltage
VDS
VGS
75
± 20
V
TC = 25 °C
4e
Continuous Drain Current (TJ = 150 °C)
TC = 70 °C
TA = 25 °C
TA = 70 °C
ID
4e
3a, b
2.4a, b
A
Pulsed Drain Current
IDM 8
Avalanche Current
Single-Pulse Avalanche Energy
L = 0.1 mH
IAS
EAS
2
0.2
mJ
TC = 25 °C
15.4
Maximum Power Dissipation
TC = 70 °C
TA = 25 °C
PD
9.9
3.1a, b
W
TA = 70 °C
2a, b
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)c, d
TJ, Tstg
- 55 to 150
260
°C
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
d. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
e. Package limited.
Document Number: 64804
S09-0661-Rev. A, 20-Apr-09
www.vishay.com
1


SIS902DN 데이터시트, 핀배열, 회로
SiS902DN
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambienta, b
Maximum Junction-to-Case (Drain)
t 10 s
Steady State
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. Maximum under Steady State conditions is 78 °C/W.
Symbol
RthJA
RthJC
Typical
32
6.4
Maximum
40
8.1
Unit
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Static
Drain-Source Breakdown Voltage
VDS
VGS = 0 V, ID = 250 µA
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
ΔVDS/TJ
ΔVGS(th)/TJ
ID = 250 µA
Gate-Source Threshold Voltage
VGS(th)
VDS = VGS, ID = 250 µA
Gate-Source Leakage
IGSS
VDS = 0 V, VGS = ± 20 V
Zero Gate Voltage Drain Current
IDSS
VDS = 75 V, VGS = 0 V
VDS = 75 V, VGS = 0 V, TJ = 55 °C
On-State Drain Currenta
ID(on)
VDS 5 V, VGS = 10 V
Drain-Source On-State Resistancea
RDS(on)
VGS = 10 V, ID = 3 A
VGS = 4.5 V, ID = 2.7 A
Forward Transconductancea
gfs VDS = 15 V, ID = 3 A
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
VDS = 38 V, VGS = 0 V, f = 1 MHz
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg VDS = 38 V, VGS = 10 V, ID = 3 A
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Qgs
Qgd
Rg
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
VDS = 38 V, VGS = 4.5 V, ID = 3 A
f = 1 MHz
VDD = 38 V, RL = 16 Ω
ID 2.4 A, VGEN = 4.5 V, Rg = 1 Ω
VDD = 38 V, RL = 16 Ω
ID 2.4 A, VGEN = 10 V, Rg = 1 Ω
Min.
75
1.2
8
Typ.
81
-5
0.155
0.190
10
Max.
Unit
2.5
± 100
1
10
0.186
0.228
V
mV/°C
V
nA
µA
A
Ω
S
175
30
18
3.9 6
2.1 3.2
0.8
0.6
0.4 2
4
17 26
18 27
12 20
9 18
5 10
8 16
10 20
6 10
pF
nC
Ω
ns
www.vishay.com
2
Document Number: 64804
S09-0661-Rev. A, 20-Apr-09




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Dual N-Channel 75-V (D-S) MOSFET - Vishay