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DMP1081UCB4 반도체 회로 부품 판매점

P-CHANNEL ENHANCEMENT MODE MOSFET



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DMP1081UCB4 데이터시트, 핀배열, 회로
DMP1081UCB4
P-CHANNEL ENHANCEMENT MODE MOSFET
Product Summary (Typ. @ VGS = -4.5V, TA = +25°C)
BVDSS
-12V
RDS(ON)
0.065Ω
Qg
2.5nC
Qgd
0.6nC
ID
-3.3A
Description
This new generation MOSFET is designed to minimize the on-state
resistance (RDS(ON)) and yet maintain superior switching performance,
making it ideal for high efficiency power management applications.
Features
LD-MOS Technology with the Lowest Figure of Merit:
RDS(ON) = 0.065to Minimize On-State Losses
Qg = 2.5nC for Ultra-Fast Switching
Vgs(TH) = -0.5V Typ. for a Low Turn-On Potential
CSP with Footprint 1.0mm × 1.0mm
Height = 0.62mm for Low Profile
ESD = 3kV HBM Protection of Gate
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Qualified to AEC-Q101 Standards for High Reliability
Applications
Battery Management
Load Switch
Battery Protection
Mechanical Data
Case: U-WLB1010-4
Terminal Connections: See Diagram Below
Weight: 0.0018 grams (Approximate)
U-WLB1010-4
DD
ESD PROTECTED TO 3kV
GS
Top View
Equivalent Circuit
Ordering Information (Note 4)
Notes:
Part Number
DMP1081UCB4-7
Case
U-WLB1010-4
Packaging
3,000/Tape & Reel
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
4. For packaging details, go to our website at http://www.diodes.com/products/packages.html.
Marking Information
U-WLB1010-4
Date Code Key
Year
Code
Month
Code
2016
D
Jan Feb
12
DMP1081UCB4
Document number: DS38597 Rev. 1 - 2
7A = Product Type Marking Code
YM = Date Code Marking
Y = Year (ex: D = 2016)
M = Month (ex: 9 = September)
2017
E
Mar
3
2018
F
Apr May
45
2019
G
Jun Jul
67
1 of 6
www.diodes.com
2020
H
Aug
8
Sep
9
2021
I
Oct
O
2022
J
Nov Dec
ND
March 2016
© Diodes Incorporated


DMP1081UCB4 데이터시트, 핀배열, 회로
Maximum Ratings (@TA = +25°C, unless otherwise specified.)
Drain-Source Voltage
Gate-Source Voltage
Characteristic
Continuous Drain Current (Note 5) VGS = -4.5V
Continuous Drain Current (Note 5) VGS = -2.5V
Pulsed Drain Current (Note 6)
Steady
State
Steady
State
TA = +25°C
TA = +70°C
TA = +25°C
TA = +70°C
Symbol
VDSS
VGSS
ID
ID
IDM
DMP1081UCB4
Value
-12
-6
-3.3
-2.7
-3.0
-2.4
20
Unit
V
V
A
A
A
Thermal Characteristics
Characteristic
Power Dissipation (Note 7)
Thermal Resistance, Junction to Ambient @TA = +25°C (Note 7)
Thermal Resistance, Junction to Case @TC = +25°C (Note 7)
Power Dissipation (Note 5)
Thermal Resistance, Junction to Ambient @TA = +25°C (Note 5)
Operating and Storage Temperature Range
Symbol
PD
RθJA
RθJC
PD
RθJA
TJ, TSTG
Value
0.82
150
42.66
1.59
80.29
-55 to +150
Unit
W
°C/W
°C/W
W
°C/W
°C
Electrical Characteristics (@TA = +25°C, unless otherwise specified.)
Characteristic
OFF CHARACTERISTICS (Note 8)
Drain-Source Breakdown Voltage
Gate-Source Breakdown Voltage
Zero Gate Voltage Drain Current TJ = +25°C
Gate-Source Leakage
ON CHARACTERISTICS (Note 8)
Gate Threshold Voltage
Static Drain-Source On-Resistance
Symbol Min Typ
BVDSS
BVGSS
IDSS
IGSS
-12
-6.0
-
-
-
-
-
-
VGS(TH)
RDS(ON)
-0.35
-
-
-
-0.5
0.065
0.077
0.108
Forward Transfer Admittance
Diode Forward Voltage
DYNAMIC CHARACTERISTICS (Note 9)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Charge at VTH
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Reverse Recovery Charge
Reverse Recovery Time
- 0.4
|Yfs| - 4
VSD - -0.6
Ciss - 213
Coss
- 119
Crss - 54.4
Qg - 2.5
Qgs - 0.3
Qgd - 0.6
Qg(TH)
- 0.15
tD(ON)
- 16.7
tR - 20.6
tD(OFF) - 38.4
tF - 28.4
QRR
- 2.0
tRR - 9.5
Notes:
5. Device mounted on FR-4 material with 1inch2 (6.45cm2), 2oz. (0.071mm thick) Cu.
6. Repetitive rating, pulse width limited by junction temperature.
7. Device mounted on FR-4 PCB with minimum recommended pad layout, single sided.
8. Short duration pulse test used to minimize self-heating effect.
9. Guaranteed by design. Not subject to production testing.
Max
-
-
-1
-100
-0.65
0.08
0.1
0.13
10
-
-1.0
350
250
90
5
-
-
-
-
-
-
-
-
-
Unit
Test Condition
V VGS = 0V, ID = -250μA
V VDS = 0V, IG = -250μA
A VDS = -9.6V, VGS = 0V
nA VGS = -6V, VDS = 0V
V VDS = VGS, ID = -250μA
VGS = -4.5V, ID = -500mA
VGS = -2.5V, ID = -500mA
VGS = -1.5V, ID = -500mA
VGS = -0.9V, ID = -100mA
S VDS = -6V, ID = -500mA
V VGS = 0V, IS = -500mA
pF
VDS = -6V, VGS = 0V,
f = 1.0MHz
nC VGS = -4.5V, VDS = -6V,
ID = -500mA
ns
VDS = -6V, VGS = -2.5V,
RG = 20Ω, ID = -500mA
nC VDD = 4.0V, IF = 0.5A,
ns di/dt =100A/μs
DMP1081UCB4
Document number: DS38597 Rev. 1 - 2
2 of 6
www.diodes.com
March 2016
© Diodes Incorporated




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P-CHANNEL ENHANCEMENT MODE MOSFET - Diodes