ADSP-218XNSERIES 반도체 회로 부품 판매점
DSP Microcomputer
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 Analog Devices |
a
DSP Microcomputer
ADSP-218xN Series
PERFORMANCE FEATURES
12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 200 CLKIN Cycle Recovery
from Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION FEATURES
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
Up to 256K Bytes of On-Chip RAM, Configured as
Up to 48K Words Program Memory RAM
Up to 56K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
SYSTEM INTERFACE FEATURES
Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to On-
Chip Memory (Mode Selectable)
4M-Byte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program and
Data Memory Transfers (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or through
Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT
Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
MEMORY
DATA ADDRESS
GENERATORS
PROGRAM
PROGRAM
MEMORY
UP TO
DATA
MEMORY
UP TO
DAG1 DAG2
Insert chip
blSoEcQkUdENiaCgErRaPmRDOAGhTReAAr4eMM8.EKMM؋EOM2RO4Y-RBAYITDADDRDER5S6ESKSS؋
PROGRAM MEMORY DATA
DATA MEMORY DATA
16-BIT
PROGRAMMABLE
I/O
AND
FLAGS
ARITHMETIC UNITS
ALU
MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT0 SPORT1
TIMER
FULL MEMORY MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
ICE-Port is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reli-
able. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. No license is granted by implication or otherwise under
any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
http://www.analog.com
Fax:781/326-8703
© Analog Devices, Inc., 2001
ADSP-218xN Series
GENERAL DESCRIPTION
The ADSP-218xN series consists of six single chip micro-
computers optimized for digital signal processing applica-
tions. The high-level block diagram for the ADSP-218xN
series members appears on the previous page. All series
members are pin-compatible and are differentiated solely by
the amount of on-chip SRAM. This feature, combined with
ADSP-21xx code compatibility, provides a great deal of
flexibility in the design decision. Specific family members
are shown in Table 1.
Table 1. ADSP-218xN DSP Microcomputer Family
Device
ADSP-2184N
ADSP-2185N
ADSP-2186N
ADSP-2187N
ADSP-2188N
ADSP-2189N
Program
Memory
(K Words)
4
16
8
32
48
32
Data Memory
(K Words)
4
16
8
32
56
48
ADSP-218xN series members combine the ADSP-2100
family base architecture (three computational units, data
address generators, and a program sequencer) with two
serial ports, a 16-bit internal DMA port, a byte DMA port,
a programmable timer, Flag I/O, extensive interrupt capa-
bilities, and on-chip program and data memory.
ADSP-218xN series members integrate up to 256K bytes
of on-chip memory configured as up to 48K words (24-bit)
of program RAM, and up to 56K words (16-bit) of data
RAM. Power-down circuitry is also provided to meet the
low power needs of battery-operated portable equipment.
The ADSP-218xN is available in a 100-lead LQFP package
and 144-Ball Mini-BGA.
Fabricated in a high-speed, low-power, 0.18 µm CMOS
process, ADSP-218xN series members operate with a
12.5 ns instruction cycle time. Every instruction can
execute in a single processor cycle.
The ADSP-218xN’s flexible architecture and comprehen-
sive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle, ADSP-218xN
series members can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
VisualDSP++ and EZ-KIT Lite are trademarks of Analog Devices, Inc.
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the
internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
DEVELOPMENT SYSTEM
Analog Devices’ wide range of software and hardware
development tools supports the ADSP-218xN series. The
DSP tools include an integrated development environment,
an evaluation kit, and a serial port emulator.
VisualDSP++™ is an integrated development environment,
allowing for fast and easy development, debug, and deploy-
ment. The VisualDSP++ project management environment
lets programmers develop and debug an application. This
environment includes an easy-to-use assembler that is based
on an algebraic syntax; an archiver (librarian/library build-
er); a linker; a PROM-splitter utility; a cycle-accurate,
instruction-level simulator; a C compiler; and a C run-time
library that
includes DSP and mathematical functions.
Debugging both C and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C and assembly code (interleaved source and
object information)
• Insert break points
• Set conditional breakpoints on registers, memory, and
stacks
• Trace instruction execution
• Fill and dump memory
• Source level debugging
The VisualDSP++ IDE lets programmers define and
manage DSP software development. The dialog boxes and
property pages let programmers configure and manage all
of the ADSP-218xN development tools, including the
syntax highlighting in the VisualDSP++ editor. This capa-
bility controls how the development tools process inputs and
generate outputs.
The ADSP-2189M EZ-KIT Lite™ provides developers
with a cost-effective method for initial evaluation of the
powerful ADSP-218xN DSP family architecture. The
ADSP-2189M EZ-KIT Lite includes a stand-alone ADSP-
2189M DSP board supported by an evaluation suite of
VisualDSP++. With this EZ-KIT Lite, users can learn
about DSP hardware and software development and evalu-
ate potential applications of the ADSP-218xN series. The
ADSP-2189M EZ-KIT Lite provides an evaluation suite of
the VisualDSP++ development environment with the
C compiler, assembler, and linker. The size of the DSP
erxecutable that can be built using the EZ-KIT Lite tools is
limited to 8K words.
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ADSP-218XNSERIES microcomputer
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