TC74VHCT573AFK 반도체 회로 부품 판매점
Octal D-Type Latch with 3-State Output
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 Toshiba |
TC74VHCT573AF/AFT/AFK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHCT573AF,TC74VHCT573AFT,TC74VHCT573AFK
Octal D-Type Latch with 3-State Output
The TC74VHCT573A is an advanced high speed CMOS OCTAL
LATCH with 3-STATE OUTPUT fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This 8-bit D-type latch is controlled by a latch enable input
(LE) and an output enable input ( OE ).
When the OE input is high, the eight outputs are in a high
impedance state.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.3
V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can
be applied to the input and output (Note) pins without regard to
the supply voltage. These structure prevents device destruction
due to mismatched supply and input/output voltages such as
battery back up, hot board insertion, etc.
Note: Output in off-state
Features
• High speed: tpd = 7.7 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• Compatible with TTL inputs: VIL = 0.8 V (max)
VIH = 2.0 V (min)
• Power down protection is provided on all inputs and outputs.
• Balanced propagation delays: tpLH ≈ tpHL
• Low noise: VOLP = 1.5 V (max)
• Pin and function compatible with the 74 series
(74AC/HC/F/ALS/LS etc.) 573 type.
TC74VHCT573AF
TC74VHCT573AFT
TC74VHCT573AFK
Weight
SOP20-P-300-1.27A:
TSSOP20-P-0044-0.65A:
VSSOP20-P-0030-0.50:
0.22 g (typ.)
0.08 g (typ.)
0.03 g (typ.)
1 2008-12-01
Pin Assignment
TC74VHCT573AF/AFT/AFK
IEC Logic Symbol
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
(top view)
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
OE (1)
LE (11)
EN
C1
D0 (2)
D1 (3)
D2 (4)
D3 (5)
D4 (6)
D5 (7)
D6 (8)
D7 (9)
1D
Truth Table
Inputs
OE LE
HX
LL
LH
LH
D
X
X
L
H
Output
Z
Qn
L
H
X: Don’t care
Z: High impedance
Qn: Q outputs are latched at the time when the LE input is taken to a low logic level.
System Diagram
(19) Q0
(18) Q1
(17) Q2
(16) Q3
(15) Q4
(14) Q5
(13) Q6
(12) Q7
D0
2
D
D1
3
D
D2
4
D
D3
5
D
D4
6
D
D5
7
D
D6
8
D
D7
9
D
11
LE
LQ LQ LQ LQ LQ LQ LQ LQ
1
OE
19 18 17 16 15 14 13 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 2008-12-01
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TC74VHCT573AFK latch
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국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈
( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )
전력반도체 문의 : 010-3582-2743
관련 데이터시트
TC74VHCT573AF
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT - Toshiba
TC74VHCT573AFK
Octal D-Type Latch with 3-State Output - Toshiba
TC74VHCT573AFT
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT - Toshiba
TC74VHCT573AFW
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT - Toshiba