TC74LVX573F 반도체 회로 부품 판매점
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT
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 Toshiba Semiconductor |
www.DataSheet4U.com
TC74LVX573F/FW/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74LVX573F,TC74LVX573FW,TC74LVX573FT
Octal D-Type Latch with 3-State Output
The TC74LVX573F/ FW/ FT is a high-speed CMOS octal latch
with 3-state output fabricated with silicon gate CMOS technology.
Designed for use in 3-V systems, it achieves high-speed operation
while maintaining the CMOS low power dissipation.
This device is suitable for low-voltage and battery operated
systems.
This 8 bit D-type latch is controlled by a latch enable input
(LE) and a output enable input (OE). When the OE input is high,
the eight outputs are in a high-impedance state.
An input protection circuit ensures that 0 to 5.5V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5V to 3V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74LVX573F
TC74LVX573FW
Features
· High speed: tpd = 6.4 ns (typ.) (VCC = 3.3 V)
· Low-power dissipation: ICC = 4 µA (max) (Ta = 25°C)
· Input voltage level: VIL = 0.8 V (max) (VCC = 3 V)
www.DataSheet4U.comVIH = 2.0 V (min) (VCC = 3 V)
TC74LVX573FT
· Power-down protection provided on all inputs
· Balanced propagation delays: tpLH ≈ tpHL
· Low noise: VOLP = 0.8 V (max)
· Pin and function compatible with 74HC573
Weight
SOP20-P-300-1.27: 0.22 g (typ.)
SOL20-P-300-1.27: 0.46 g (typ.)
TSSOP20-P-0044-0.65: 0.08 g (typ.)
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1 2002-01-16
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Pin Assignment (top view)
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
TC74LVX573F/FW/FT
IEC Logic Symbol
(1)
OE
(11)
LE
EN
C1
(2)
D0
(3)
D1
(4)
D2
(5)
D3
(6)
D4
(7)
D5
(8)
D6
(9)
D7
1D
(19)
Q0
(18)
Q1
(17)
Q2
(16)
Q3
(15)
Q4
(14)
Q5
(13)
Q6
(12)
Q7
Truth Table
Inputs
OE LE
D
Outputs
HXX
Z
L LX
Qn
L H wwL w.DaLtaSheet4U.com
L HH
H
X: Don’t care
Z: High impedance
Qn: Q outputs are latched at the time when the LE input is taken to a low logic level.
System Diagram
D0
2
D
D1
3
D
D2
4
D
D3
5
D
D4
6
D
D5
7
D
D6
8
D
D7
9
D
11
LE
1
OE
QQQQQQQQ
LLLLLLLL
19 18 17 16 15 14 13 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
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2 2002-01-16
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제조업체: Toshiba Semiconductor
( toshiba )
TC74LVX573F latch
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국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
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관련 데이터시트
TC74LVX573F
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT - Toshiba Semiconductor
TC74LVX573FT
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT - Toshiba Semiconductor
TC74LVX573FW
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT - Toshiba Semiconductor