CD54ACT5733A 반도체 회로 부품 판매점
Octal Transparent Latch Three-State/ Non-Inverting
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 Intersil |
SEMICONDUCTOR
June 1997
COMPLETE DATA SHEET
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CD54AC573/3A
CD54ACT573/3A
Octal Transparent Latch
Three-State, Non-Inverting
Description
Functional Diagram
The CD54AC573/3A and CD54ACT573/3A are octal trans-
parent three-state latches that utilize the Harris Advanced
CMOS Logic technology. The outputs are transparent to the
inputs when the Latch Enable (LE) is HIGH. When the Latch
Enable (LE) goes LOW, the data is latched. The Output
Enable (OE) controls the three-state outputs. When the Out-
put Enable (OE) is HIGH, the outputs are in the high-imped-
ance state. The latch operation is independent of the state of
the Output Enable.
The CD54AC573/3A and CD54ACT573/3A are supplied in
20 lead dual-in-line ceramic packages (F suffix).
D0
D1
D2
D3
D4
D5
D6
ACT INPUT LOAD TABLE
INPUT
UNIT LOAD (NOTE 1)
OE 0.87
Dn 0.5
LE 0.8
NOTE:
1. Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA Max at +25oC.
D7
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current, Per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or GND Current, ICC or IGND
For Up to 4 Outputs Per Device, Add ±25mA For Each
Additional Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±100mA
Power Dissipation Per Package, PD
TA = -55oC to +100oC (Package F) . . . . . . . . . . . . . . . . . . 500mW
TA = +100oC to +125oC (Package F) . . . . . . . . Derate Linearly at
8mW/oC to 300mW
Operating Temperature Range, TA
Package Type F . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Storage Temperature, TSTG . . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering)
At Distance 1/16in. ± 1/32in. (1.59mm ± 0.79mm)
From Case For 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Unit Inserted Into a PC Board (Min Thickness 1/16in., 1.59mm)
With Solder Contacting Lead Tips Only. . . . . . . . . . . . . . . +300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
Supply Voltage Range, VCC
Unless Otherwise Specified, All Voltages Referenced to GND
TA = Full Package Temperature Range
CD54AC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
CD54ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO. . . . . . . . . . . . . . . . . . 0V to VCC
Operating Temperature, TA . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Input Rise and Fall Slew Rate, dt/dv
at 1.5V to 3V (AC Types) . . . . . . . . . . . . . . . . . . . 0ns/V to 50ns/V
at 3.6V to 5.5V (AC Types) . . . . . . . . . . . . . . . . . 0ns/V to 20ns/V
at 4.5V to 5.5V (AC Types) . . . . . . . . . . . . . . . . . 0ns/V to 10ns/V
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1994
1
File Number 3915
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CD54ACT5733A latch
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관련 데이터시트
CD54ACT5733A
Octal Transparent Latch Three-State/ Non-Inverting - Intersil Corporation
CD54ACT5733A
Octal Transparent Latch Three-State/ Non-Inverting - Intersil