74LCX16841MEA 반도체 회로 부품 판매점
Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
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 Fairchild Semiconductor |
October 1995
Revised April 1999
74LCX16841
Low Voltage 20-Bit Transparent Latch with 5V Tolerant
Inputs and Outputs
General Description
The LCX16841 contains twenty non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCX16841 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment.
The LCX16841 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 5.5 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX16841MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCX16841MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
LEn
D0–D19
O0–O19
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
© 1999 Fairchild Semiconductor Corporation DS012578.prf
www.fairchildsemi.com
Connection Diagram
Truth Tables
Inputs
Outputs
LE1
OE1
D0–D9
O0–O9
XHXZ
HL L L
H L HH
L L X O0
Inputs
Outputs
LE2 OE2 D10–D19 O10–O19
XHXZ
HL L L
H L HH
L L X O0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Functional Description
The LCX16841 contains twenty D-type latches with 3-
STATE standard outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
20-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the Dn enters the latches. In this condition the latches are
transparent, i.e. a latch output will change states each time
Logic Diagrams
its D input changes. When LEn is LOW, the latches store
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LEn. The 3-
STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard out-
puts are in the 2-state mode. When OEn is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and Outputs - Fairchild Semiconductor
