SCAN18373T 반도체 회로 부품 판매점
Transparent Latch with TRI-STATE Outputs
|
|
 National Semiconductor |
September 1998
SCAN18373T
Transparent Latch with TRI-STATE® Outputs
General Description
The SCAN18373T is a high speed, low-power transparent
latch featuring separate data inputs organized into dual 9-bit
bytes with byte-oriented latch enable and output enable con-
trol signals. This device is compliant with IEEE 1149.1 Stan-
dard Test Access Port and Boundary Scan Architecture with
the incorporation of the defined boundary-scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TDO), Test Mode Select (TMS), and Test Clock
(TCK).
Features
n IEEE 1149.1 (JTAG) Compliant
n Buffered active-low latch enable
n TRI-STATE outputs for bus-oriented applications
n 9-bit data busses for parity applications
n Reduced-swing outputs source 24 mA/sink 48 mA
n Guaranteed to drive 50Ω transmission line to TTL input
levels of 0.8V and 2.0V
n TTL compatible inputs
n 25 mil pitch Cerpack packaging
n Includes CLAMP and HIGHZ instructions
n Standard Microcircuit Drawing (SMD) 5962-9311801
Connection Diagram
DS100321-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100321
Pin Names
AI(0–8), BI(0–8)
ALE, BLE
AOE1, BOE1
AO(0–8), BO(0–8)
Description
Data Inputs
Latch Enable Inputs
TRI-STATE Output Enable Inputs
TRI-STATE Latch Outputs
Truth Tables
ALE
X
H
H
L
Inputs
AOE1
H
L
L
L
AI (0–8)
X
L
H
X
Inputs
BLE
X
BOE1
H
BI (0–8)
X
HL
L
HL
H
LL
X
H= HIGH Voltage Level
L= LOW Voltage Level
X= Immaterial
Z= High Impedance
AO0 = Previous AO before H-to-L transition of ALE
BO0 = Previous BO before H-to-L transition of BLE
AO (0–8)
Z
L
H
AO0
BO (0–8)
Z
L
H
BO0
Functional Description
The SCAN18373T consists of two sets of nine D-type
latches with TRI-STATE standard outputs. When the Latch
Enable (ALE or BLE) input is HIGH, data on the inputs
(AI(0–8) or BI(0–8) ) enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its input changes. When Latch Enable is LOW, the
latches store the information that was present on the inputs
a set-up time preceding the HIGH-to-LOW transition of the
www.national.com
Functional Description (Continued)
Latch Enable. The TRI-STATE standard outputs are con-
trolled by the Output Enable (AOE1 or BOE1) input. When
Output Enable is LOW, the standard outputs are in the
Logic Diagram
2-state mode. When Output Enable is HIGH, the standard
outputs are in the high impedance mode, but this does not
interfere with entering new data into the latches.
DS100321-13
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Block Diagrams
Byte-A
DS100321-2
www.national.com
2
|
PDF 파일 내의 페이지 : 총 14 페이지
제조업체: National Semiconductor
( national )
SCAN18373T latch
데이터시트 다운로드 :
[ SCAN18373T.PDF ]
[ SCAN18373T 다른 제조사 검색 ]
국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈
( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )
전력반도체 문의 : 010-3582-2743
관련 데이터시트
SCAN18373T
Transparent Latch with TRI-STATE Outputs - National Semiconductor
SCAN18373T
SCAN18373T Transparent Latch with TRI-STATE Outputs (Rev. B) - Texas Instruments