|
Richtek |
®
RT8901
35V Gate Pulse Modulator for LCD Panels
General Description
The Gate Pulse Modulator (GPM) is specially designed
for the application of gate driver in TFT LCD panels. The
GPM is controlled by frame signals from timing controller
to modulate the Gate-On voltage that acts a flicker
compensation circuit to reduce the coupling effect between
gate lines and pixels. It also can delay the Gate-On voltage
while power-on for achieving a correct power-on-sequence
for gate driver ICs. Both of the delay time for flicker
compensation and power-on-sequence are programmable
by external resistors and capacitors.
Features
Flicker Compensation Circuit
Reduction of Coupling Effect Between Gate Line
and Pixel
Programmable Power Sequence for Gate Driver IC
Operation from 20V to 35V Positive Supply Input
Adjustable Output Delay Time
RoHS Compliant and 100% Lead (Pb)-Free
Applications
TFT-LCDPanels
Ordering Information
RT8901
Typical Application Circuit
Package Type
S : SOP-8
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
VCD
VFLK
VDPM
4 CD
VGH 1
RT8901
8 VFLK
VGH
C1
1µF
R2
33k
6 VDPM
VGHM 2
R1
C3
100pF
RE 3 1.2k
VGHM
C2
1.5nF
7 GND
VD 5
R5A 200k
VAVDD
R5B
20k
Marking Information
RT8901GS
RT8901GS : Product Number
RT8901
GSYMDNN
YMDNN : Date Code
Pin Configurations
(TOP VIEW)
VGH
VGHM
RE
CD
2
3
4
8 VFLK
7 GND
6 VDPM
5 VD
Figure 1. Typical Application Circuit for Mode A and
Mode C
VFLK
VDPM
C4
100pF 4 CD
VGH 1
8
RT8901
VFLK
R2
33k
6 VDPM
VGHM 2
R1
C3
100pF
RE 3 1.2k
VGH
C1
1µF
VGHM
C2
1.5nF
7 GND
VD 5
R5A 200k
VAVDD
R5B
20k
SOP-8
Figure 2. Typical Application Circuit for Mode B
Copyright ©2013 Richtek Technology Corporation. All rights reserved.
DS8901-03 October 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8901
Timing Diagram
VGH
VDPM 0V
CD
VFLK
VGH
High
VREF
VCD = 5V
Low
VGHM
0V
10VD
Duty is controlled by VFLK
Discharging Time
is controlled by R1
Figure 3. Timing Sequence of Mode A
VGH
VDPM 0V
CD
VFLK
VREF
0.9VDD
VREF
VGH
VGHM
0V
10VD
Duty is controlled by VFLK and C4
Discharging Time
is controlled by R1
Figure 4. Timing Sequence of Mode B
VGH
VDPM 0V
CD
VFLK
VGH
High
VREF
VCD = 3.3V
Low
VGHM
0V
10VD
Duty is controlled by VFLK
Discharging Time
is controlled by R1
Figure 5. Timing Sequence of Mode C
Copyright ©2013 Richtek Technology Corporation. All rights reserved.
www.richtek.com
2
is a registered trademark of Richtek Technology Corporation.
DS8901-03 October 2013
|