NLHV001 반도체 회로 부품 판매점
1-Bit Gate Pulse Modulator
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 ON Semiconductor |
NLHV001
1-Bit Gate Pulse Modulator
The NLHV001 is a 1−bit gate pulse modulator designed to translate
logic voltages for TFT LCD panels. This part translates a low voltage
logic input signal to an output voltage of 15 V to 38 V. In addition, the
NLV001 provides a user selectable delay and fall time on the
high−to−low edge of the output signal. The delay and fall times are
controlled by the magnitudes of the external and capacitor resistor,
respectively.
Features
• Gate Pulse Modulation (GPM)
• TFT LCD Flicker Compensation Circuit
• Reduction of Coupling Effect Between Gate Line and Pixel
• Provides Power Sequencing Circuit for Gate Driver IC
• Wide Power Supply Operation: 15 V to 38 V
• Adjustable Output Delay and Fall Time
• This is a Pb−Free Device
Typical Applications
• TFT LCDs
Important Information
• ESD Protection for All Pins:
Human Body Model (HBM) > 3000 V
VGH
1
VGH_M
2
High Voltage
Power Supply
High
Voltage
Output
Signal
Low
Voltage
Input
Signal
VFLK
8
GND
7
http://onsemi.com
MARKING
DIAGRAM
8
US8
US SUFFIX
CASE 493
AL M G
G
1
AL = Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending upon
manufacturing location.
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
RE
3
CE
4
Falling
Edge
Control
Low Voltage
Power Supply
Propagation
Delay Control
VDPM
6
VDD
5
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 0
1
Publication Order Number:
NLHV001/D
NLHV001
PIN DESCRIPTION
Pin Pin Name
1 VGH
2 VGH_M
3 RE
4 CE
5 VDD
6 VDPM
7 GND
8 VFLK
Pin Function
Power Supply Input
Output
RE pin used to set the falling edge
time (tfall)
CE pin used to set the propagation
delay time (tphl)
Reference to input
Signal input 1
Ground
Signal input 2
Comment
VGH = 15 to 38 V
This output directly drives the power supply of Gate Driver IC
The Delay time is programmed by connecting resistor RE to VGH
and capacitor CE to ground.
The reference input pin is used to reduce flicker. The reference
input voltage is as follows:
VDD ≤ VGH – 8.5 V, VDD = 0 to 25 V
VVDDPPMM
single input voltage
= 0 V to VGH.
is
as
follows:
The VDPM pin is used to create a delay with the VGH to prevent
system latch−up. VDPM also determines the time VGH is ON.
VFLK single input voltage is as follows:
VDPM = 0 V to VGH.
The VFLK determines the ON/OFF time of the TFT LCD and is pro-
duced from LCD timing controller module.
Figure 2. Block Diagram
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2
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NLHV001 gate
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