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Hitachi Semiconductor |
HD74HC125/HD74HC126
Quad. Bus Buffer Gates (with 3-state outputs)
Description
The HD74HC125, HD74HC126 require the 3-state control input C to be taken high to put the output into
the high impedance condition, whereas the HD74HC125, HD74HC126 requires the control input to be low
to put the output into high impedance.
Features
• High Speed Operation: tpd = 8 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
C
HC125
HC126
A
HL
X
LH
L
LH
H
X : Irrelevent
Z : Off (high-impedance) state of a 3-state output.
Output Y
HC125
Z
L
H
HC126
Z
L
H
HD74HC125/HD74HC126
Pin Arrangement
HD74HC125
HD74HC126
1C 1
1A 2
1Y 3
2C 4
2A 5
2Y 6
GND 7
(Top view)
14 VCC
13 4C
12 4A
11 4Y
10 3C
9 3A
8 3Y
1C 1
1A 2
1Y 3
2C 4
2A 5
2Y 6
GND 7
(Top view)
14 VCC
13 4C
12 4A
11 4Y
10 3C
9 3A
8 3Y
2
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