MC74HC10A 반도체 회로 부품 판매점
Triple 3-Input NAND Gate High-Performance Silicon-Gate CMOS
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MC74HC10A
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Triple 3-Input NAND Gate
High−Performance Silicon−Gate CMOS
The MC74HC10A is identical in pinout to the LS10. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the Requirements Defined JEDEC
Standard No. 7 A
• Chip Complexity: 36 FETs or 9 Equivalent Gates
• Pb−Free Packages are Available
LOGIC DIAGRAM
1
A1
2
B1
13
C1
12
Y1
3
A2
4
B2
5
C2
6
Y2
9
A3
10
B3
11
C3
8
Y3
PIN 14 = VCC
PIN 7 = GND
Y = ABC
PIN ASSIGNMENT
A1 1
B1 2
A2 3
B2 4
C2 5
Y2 6
GND 7
14 VCC
13 C1
12 Y1
11 C3
10 B3
9 A3
8 Y3
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14
1
14
1
MARKING
DIAGRAMS
14
PDIP−14
N SUFFIX
CASE 646
1
MC74HC10AN
AWLYYWWG
14
SOIC−14
D SUFFIX
CASE 751A
1
HC10AG
AWLYWW
14
1
TSSOP−14
DT SUFFIX
CASE 948G
14
HC
10A
ALYWG
G
1
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output
AB
Y
LL
LH
HL
HH
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 1
1
Publication Order Number:
MC74HC10A/D
MC74HC10A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
Vin DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5 V
Vout DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5 V
Iin DC Input Current, per Pin
± 20 mA
Iout DC Output Current, per Pin
± 25 mA
ICC DC Supply Current, VCC and GND Pins
± 50 mA
PD Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
Tstg Storage Temperature
– 65 to + 150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
260
_C
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Max Unit
VCC
Vin, Vout
TA
tr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
2.0
0
– 55
0
0
0
0
6.0
VCC
+ 125
1000
600
500
400
V
V
_C
ns
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This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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MC74HC10A gate
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