TH58NVG1S3AFT05 반도체 회로 부품 판매점
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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 Toshiba Semiconductor |
TH58NVG1S3AFT05
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2GBIT (256M u 8BITS) CMOS NAND E2PROM
DESCRIPTION
The TH58NVG1S3A is a single 3.3-V 2G-bit (2,214,592,512 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (2048+64) bytes x 64 pages x 2048 blocks.
The device has a 2112-byte static registers which allow program and read data to be transferred
between the register and the memory cell array in 2112-byte increments. The Erase operation is
implemented in a single block unit (128 Kbytes + 4Kbytes: 2112 bytes x 64 pages).
The TH58NVG1S3A is a serial-type memory device which utilizes the I/O pins for both address and data
input / output as well as for command inputs. The Erase and Program operations are automatically
executed making the device most suitable for applications such as solid-state file storage, voice
recording, image file memory for still cameras and other systems which require high-density non-
volatile memory data storage.
FEATURES
x Organization
Memory cell allay 2112 u 64K u 8 u 2
Register
2112 u 8
Page size
2112bytes
Block size
(128K 4K) bytes
x Modes
Read㧘Reset㧘Auto Page Program
Auto Block Erase㧘Status Read
x Mode control
Serial input㧛output
Command control
PIN ASSIGNMENT (TOP VIEW)
x Powersupply
VCC 2.7 V to 3.6 V
x Program/Erase Cycles
1E5 Cycles(With ECC)
x Access time
Cell array to register 25 Psmax
Serial Read Cycle
50 ns min
x Operating current
Read (50 ns cycle)
10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
50 PA max
x Package
TSOP I 48-P-1220-0.50
(Weight : 0.53 g typ.)
PIN NAMES
NC
NC
NC
NC
NC
GND
RY/BY
RE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 NC
47 NC
46 NC
45 NC
44 I/O8
43 I/O7
42 I/O6
41 I/O5
40 NC
39 NC
38 NC
37 VCC
36 VSS
35 NC
34 NC
33 NC
32 I/O4
31 I/O3
30 I/O2
29 I/O1
28 NC
27 NC
26 NC
25 NC
I/O1 to I/O8
CE
WE
RE
CLE
ALE
WP
RY / BY
GND
VCC
VSS
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready / Busy
Ground Input
Power supply
Ground
000707EBA1
xTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
xThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at
the customer’s own risk.
2003-05-19A 1/32
BLOCK DIAGRAM
I/O1
to
I/O8
CE
CLE
ALE
WE
RE
WP
RY / BY
I/O
Control
circuit
Logic
control
RY / BY
TH58NVG1S3AFT05
Status register
Address register
Command register
Control
circuit
VCC VSS
Column buffer
Column decoder
Data register
Sense amp
Memory
cell array
HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
VCC
VIN
VI/O
PD
TSOLDER
TSTG
TOPR
Power Supply Voltage
Input Voltage
Input /Output Voltage
Power Dissipation
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
VALUE
0.6 to 4.6
0.6 to 4.6
0.6 V to VCC 0.3 V ( 4.6 V)
0.3
260
-55 to 150
0 to 70
CAPACITANCE *(Ta 25°C, f 1 MHz)
SYMB0L
PARAMETER
CONDITION
CIN Input
VIN 0 V
COUT
Output
VOUT 0 V
* * This parameter is periodically sampled and is not tested for every device.
MIN
MAX
20
20
UNIT
V
V
V
W
°C
°C
°C
UNIT
pF
pF
xThe products described in this document are subject to the foreign exchange and foreign trade laws.
xThe information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
xThe information contained herein is subject to change without notice.
2003-05-19A 2/32
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TH58NVG1S3AFT05 gate
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TH58NVG1S3AFT05
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS - Toshiba Semiconductor
