MC14025B 반도체 회로 부품 판매점
B-Suffix Series CMOS Gates
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 Motorola Semiconductors |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
B-Suffix Series CMOS Gates
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
• Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
• Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix
Devices (Exceptions: MC14068B and MC14078B)
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
MC14XXXBD
Ceramic
SOIC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA = – 55° to 125°C for all packages.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎlin, lout
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Input or Output Current (DC or Transient),
per Pin
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
± 10
V
V
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation, per Package†
500 mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
– 65 to + 150
_C
TL Lead Temperature (8–Second Soldering)
260 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14001B
Quad 2-Input NOR Gate
MC14002B
Dual 4-Input NOR Gate
MC14011B
Quad 2-Input NAND Gate
MC14012B
Dual 4-Input NAND Gate
MC14023B
Triple 3-Input NAND Gate
MC14025B
Triple 3-Input NOR Gate
MC14068B
8-Input NAND Gate
MC14071B
Quad 2-Input OR Gate
MC14072B
Dual 4-Input OR Gate
MC14073B
Triple 3-Input AND Gate
MC14075B
Triple 3-Input OR Gate
MC14078B
8-Input NOR Gate
MC14081B
Quad 2-Input AND Gate
MC14082B
Dual 4-Input AND Gate
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14001B
7
NOR
MC14001B
Quad 2–Input NOR Gate
LOGIC DIAGRAMS
NAND
MC14011B
Quad 2–Input NAND Gate
OR
MC14071B
Quad 2–Input OR Gate
AND
MC14081B
Quad 2–Input AND Gate
1
3
2
5
4
6
8
9 10
12
11
13
MC14025B
Triple 3–Input NOR Gate
1
29
8
3
46
5
11
12 10
13
MC14002B
Dual 4–Input NOR Gate
2
3
4
1
5
9
10
11
13
12
NC = 6, 8
MC14078B
8–Input NOR Gate
2
3
4
5
9
13
10
11
12 NC = 6, 8
1
3
2
5
4
6
8
9 10
12
11
13
MC14023B
Triple 3–Input NAND Gate
1
29
8
3
46
5
11
12 10
13
MC14012B
Dual 4–Input NAND Gate
2
3
4
1
5
9
10
11
13
12
NC = 6, 8
MC14068B
8–Input NAND Gate
2
3
4
5
9
13
10
11
12 NC = 6, 8
1
3
2
5
4
6
8
9 10
12
11
13
MC14075B
Triple 3–Input OR Gate
1
29
8
3
46
5
11
12 10
13
MC14072B
Dual 4–Input OR Gate
2
3
4
1
5
9
10
11
13
12
NC = 6, 8
1
3
2
5
4
6
8
9 10
12
11
13
MC14073B
Triple 3–Input AND Gate
1
29
8
3
46
5
11
12 10
13
MC14082B
Dual 4–Input AND Gate
2
3
4
1
5
9
10
11
13
12
NC = 6, 8
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
MC14001B
8
MOTOROLA CMOS LOGIC DATA
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MC14025B gate
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