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Toshiba |
rOSHIBA
TC518512PL/FL/FIL/TRL-70(DR) /80 (DR) /10 (DR)
SILICON GATE CMOS
524,288 WORD x 8 BIT CMOS PSEUDO STATIC RAM
Description
The TC518512PL is a 4M bit high speed CMOS pseudo static RAM organized as 524,288 words by 8 bits. The TC518512PL utilizes
a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, .!J!gh speed and low power storage. The
TC518512PL operates from a single 5V power supply. Refreshing is supported by a refresh (OEIRFSH) input which enables two
types of refreshing - auto refresh and self refresh. The TC518512PL features a static RAM-like interface with a write cycle in which
the input data is written into the memory cell at the rising edge of RNV thus simplifying the microprocessor interface.
The TC518512PL is available in a 32-pin, 0.6 inch width plastic DIP, a small outline plastic flat package, and a thin small outline
package (forward type, reverse type).
Features
• Organization: 524,288 words x 8 bits
• Single 5V power supply
• Data retention supply voltage: 3.0V - 5.5V
• Fast access time
TC518512PL-(DR) Family
crtCEA Access Time
toEA OE Access Time
tRC Cycle Time
Power Dissipation
!S.SV
Self Refresh Current !
3.0V
-70
70ns
30ns
11Sns
38SmW
·80
80ns
30ns
130ns
330mW
200!lA
100!lA
·10
100ns
40ns
160ns
27SmW
• Auto refresh is supported by an internal refresh address
counter
• Self refresh is supported by an internal timer
• Inputs and outputs TIL compatible
• Refresh: 2048 refresh cycles/32ms
Ala
Al6
Al4
Al2
A7
A6
AS
A4
A3
A2
Al
AO
1/01
1/02
1103
GNO
Voo
A1S
Al7
R/VV
Al0
Ct
1/08
1107
1/06
1/05
1104
Ala
A16
Al4
Al2
A7
A6
AS
A4
A3
A2
Al
AO
1/01
1/02
1/03
GNO
• Package
- TC518512PL: DIP32-P-600
- TC518512FL: SOP32-P-525
• TC518512FTL: TSOP32-P-400
• TC518512TRL: TSOP32-P-400A
Pin Names
AO - A18 Address Inputs
R/W
ReadJWrite Control Input
OE/RrnR
CE
Output Enable Input
Refresh Input
Chip Enable Input
1/01 -1108 Data Inputs/Outputs
Voo
GND
Power
Ground
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
0-175
TC51S512PL/FL/FTLlTRL-70(DR)/SO(DR)/10(DR) Static RAM
Block Diagram
Voo
COLUMN
DECODER
MEMORY
ARRAY
204Sx 256xS
REFRESH
TIMER
,co
o
,o
RIW 0----<3
Operating Mode
~MODE
Read
Write
~ only Refresh
Auto/Self Refresh
Standby
CE
L
L
L
H
H
DEI
RFSH
L
*
H
L
H
R/W AD -A18 1/01 - 8
H V* OUT
L V* IN
H V* HZ
* * HZ
* * HZ
H = High level input (VIH)
L = Low level input (VIU
• =V1H orVIL
V* = At the falling edge of CE, ali address inputs are latched. At ali other times, the address inputs are "*".
HZ =High impedance
Maximum Ratings
SYMBOL
ITEM
VIN Input Voltage
Your Output Voltage
Voo Power Supply Voltage
TOPR Operating Temperature
TSTRG Storage Temperature
TSOLOER Soldering Temperature' Time
Po Power Dissipation
lOUT Short Circuit Output Current
RATING
-1.0 - 7.0
-1.0 -7.0
-1.0 - 7.0
0-70
-55 - 150
260·10
600
50
UNIT NOTES
V
V
V
°C
°C
°C· sec
mW
1
mA
0-176
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
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