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TC74AC08FN 반도체 회로 부품 판매점

Quad 2-Input AND Gate



Toshiba 로고
Toshiba
TC74AC08FN 데이터시트, 핀배열, 회로
www.DataSheet4U.com
TC74AC08P/F/FN/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC08P,TC74AC08F,TC74AC08FN,TC74AC08FT
Quad 2-Input AND Gate
The TC74AC08 is an advanced high speed CMOS 2-INPUT
AND GATE fabricated with silicon gate and double-layer metal
wiring C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 2 stages including buffer
output, which provide high noise immunity and stable output.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
High speed: tpd = 3.4 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 µA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Symmetrical output impedance:
|IOH| = IOL = 24 mA (min)
Capability of driving 50 transmission lines.
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2DVattoa5S.5heVet4U.com
Pin and function compatible with 74F08
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74AC08P
TC74AC08F
DataShee
TC74AC08FN
DataSheet4U.com
DataSheet4 U .com
Weight
DIP14-P-300-2.54
: 0.96 g (typ.)
SOP14-P-300-1.27A : 0.18 g (typ.)
SOP14-P-300-1.27
: 0.18 g (typ.)
SOL14-P-150-1.27
: 0.12 g (typ.)
TSSOP14-P-0044-0.65A : 0.06 g (typ.)
TC74AC08FT
1
2006-02-01


TC74AC08FN 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Pin Assignment
TC74AC08P/F/FN/FT
IEC Logic Symbol
et4U.com
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
(top view)
Truth Table
ABY
LLL
L HL
HLL
HHH
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
1A (1)
1B (2)
2A (4)
2B (5)
3A (9)
3B (10)
4A (12)
4B (13)
&
(3) 1Y
(6) 2Y
(8) 3Y
(11) 4Y
Absolute Maximum Ratings (Note 1)
DataSheet4U.com
Characteristics
Symbol
Rating
Unit
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC VCC/ground current
Power dissipation
Storage temperature
VCC
VIN
VOUT
IIK
IOK
IOUT
ICC
PD
Tstg
0.5 to 7.0
0.5 to VCC + 0.5
0.5 to VCC + 0.5
±20
±50
±50
±100
500 (DIP) (Note 2)/180 (SOP/TSSOP)
65 to 150
V
V
V
mA
mA
mA
mA
mW
°C
Note1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Note2: 500 mW in the range of Ta = 40°C to 65°C. From Ta = 65°C to 85°C a derating factor of 10 mW/°C
should be applied up to 300 mW.
DataShee
DataSheet4U.com
DataSheet4 U .com
2 2006-02-01




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TC74AC08FN gate

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TC74AC08F

Quad 2-Input AND Gate - Toshiba Semiconductor



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TC74AC08FT

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