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NC7SZ74K8X 반도체 회로 부품 판매점

TinyLogic UHS D-Type Flip-Flop with Preset and Clear



Fairchild 로고
Fairchild
NC7SZ74K8X 데이터시트, 핀배열, 회로
July 2001
Revised June 2003
NC7SZ74
TinyLogicUHS D-Type Flip-Flop with Preset and Clear
General Description
The NC7SZ74 is a single D-type CMOS Flip-Flop with pre-
set and clear from Fairchild’s Ultra High Speed Series of
TinyLogicin the space saving US8 package. The device
is fabricated with advanced CMOS technology to achieve
ultra high speed with high output drive while maintaining
low static power dissipation over a very broad VCC operat-
ing range. The device is specified to operate over the
1.65V to 5.5V VCC range. The inputs and output are high
impedance when VCC is 0V. Inputs tolerate voltages up to
7V independent of VCC operating voltage. The output toler-
ates voltages above VCC in the 3-STATE condition.
The signal level applied to the D input is transferred to the
Q output during the positive going transition of the CLK
pulse.
Features
s Space saving US8 surface mount package
s MicroPakleadless package
s Ultra High Speed; tPD 2.6 ns Typ into 50 pF at 5V VCC
s High Output Drive; ± 24 mA at 3V VCC
s Broad VCC Operating Range; 1.65V to 5.5V
s Power down high impedance inputs/output
s Overvoltage tolerant inputs facilitate 5V to 3V translation
s Patented noise/EMI reduction circuitry implemented
Ordering Code:
Order Package
Number Number
NC7SZ74K8X MAB08A
NC7SZ74L8X MAC08A
Product
Code
Top Mark
Z74
N9
Package Description
Supplied As
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
TinyLogicis a registered trademark of Fairchild Semiconductor Corporation.
MicroPakis a trademark of Fairchild Semiconductor Corporation.
© 2003 Fairchild Semiconductor Corporation DS500499
www.fairchildsemi.com


NC7SZ74K8X 데이터시트, 핀배열, 회로
Logic Symbol
IEEE/IEC
Connection Diagrams
Pin Descriptions
Pin Names
D
CK
CLR
Q, Q
PR
Description
Data Input
Clock Pulse Input
Direct Clear Input
Flip-Flop Output
Direct Preset Input
(Top View)
Pin One Orientation Diagram
Truth Table
Inputs
CLR
L
H
L
H
H
PR
H
L
L
H
H
D
X
X
X
L
H
HHX
H = HIGH Logic Level
L = LOW Logic Level
Qn = No change in data
Z = High Impedance
X = Immaterial
↑ = Rising Edge
↓ = Falling edge
Outputs
AAA represents Product Code Top Mark - see ordering code
CK Q
Q
Function
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
X L H Clear
X H L Preset
Pad Assignments for MicroPak
XHH
LH
HL
Qn Qn No Change
(Top Thru View)
www.fairchildsemi.com
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NC7SZ74K8X flip-flop

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