100331 반도체 회로 부품 판매점
Low Power Triple D-Type Flip-Flop
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 Fairchild Semiconductor |
February 1990
Revised August 2000
100331
Low Power Triple D-Type Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CPC), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CPn),
Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters
a master when both CPn and CPC are LOW and transfers
to a slave when CPn or CPC (or both) go HIGH. The Master
Set, Master Reset and individual CDn and SDn inputs over-
ride the Clock inputs. All inputs have 50 kΩ pull-down
resistors.
Features
s 35% power reduction of the 100131
s 2000V ESD protection
s Pin/function compatible with 100131
s Voltage compensated operating range = −4.2V to −5.7V
s Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
100331SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100331PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100331QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100331QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names
CP0–CP2
CPC
D0–D2
CD0–CD2
SDn
MR
MS
Q0-Q2
Q0–Q2
Description
Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS010262
28-Pin PLCC
www.fairchildsemi.com
Truth Tables
Synchronous Operation (Each Flip-Flop)
Inputs
MS MR
Dn
CPn
CPC
SDn
CDn
L L L L
H L L L
L L
LL
H L
LL
XLLLL
XHXL L
XXHL L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
U = Undefined
t = Time before CP Positive Transition
t + 1 = Time after CP Positive Transition
= LOW-to-HIGH Transition
Outputs
Qn(t + 1)
L
H
L
H
Qn(t)
Qn(t)
Qn(t)
Logic Diagram
Asynchronous Operation (Each Flip-Flop)
Inputs
MS MR
Dn
CPn
CPC
SDn
CDn
XXXHL
XXXLH
XXXHH
Outputs
Qn(t + 1)
H
L
U
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제조업체: Fairchild Semiconductor
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100331 flip-flop
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[ 100331.PDF ]
[ 100331 다른 제조사 검색 ]
국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
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전력반도체 문의 : 010-3582-2743
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