IR2132J 반도체 회로 부품 판매점
3-PHASE BRIDGE DRIVER
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 International Rectifier |
Data Sheet No. PD60019 Rev.P
IR2130/IR2132(J)(S) & (PbF)
3-PHASE BRIDGE DRIVER
Features
• Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
• Gate drive supply range from 10 to 20V
• Undervoltage lockout for all channels
• Over-current shutdown turns off all six drivers
• Independent half-bridge drivers
• Matched propagation delay for all channels
• 2.5V logic compatible
• Outputs out of phase with inputs
• Cross-conduction prevention logic
• Also available LEAD-FREE
Description
Product Summary
VOFFSET
600V max.
IO+/-
200 mA / 420 mA
VOUT
10 - 20V
ton/off (typ.)
675 & 425 ns
Deadtime (typ.) 2.5 µs (IR2130)
0.8 µs (IR2132)
Packages
The IR2130/IR2132(J)(S) is a high voltage, high speed
power MOSFET and IGBT driver with three indepen-
dent high and low side referenced output channels. Pro-
prietary HVIC technology enables ruggedized
monolithic construction. Logic inputs are compatible with
28-Lead SOIC
CMOS or LSTTL outputs, down to 2.5V logic. A
ground-referenced operational amplifier provides
28-Lead PDIP
analog feedback of bridge current via an external cur-
rent sense resistor. A current trip function which termi-
nates all six outputs is also derived from this resistor.
44-Lead PLCC w/o 12 Leads
An open drain FAULT signal indicates if an over-cur-
rent or undervoltage shutdown has occurred. The output drivers feature a high pulse current buffer stage designed
for minimum driver cross-conduction. Propagation delays are matched to simplify use at high frequencies. The
floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration
which operate up to 600 volts.
Typical Connection
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer
to our Application Notes and DesignTips for proper circuit board layout.
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1
IR2130/IR2132(J)(S) & (PbF)
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to VS0. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 50 through 53.
Symbol
Definition
Min.
Max. Units
VB1,2,3
VS1,2,3
VHO1,2,3
VCC
VSS
VLO1,2,3
VIN
High Side Floating Supply Voltage
High Side Floating Offset Voltage
High Side Floating Output Voltage
Low Side and Logic Fixed Supply Voltage
Logic Ground
Low Side Output Voltage
Logic Input Voltage (HIN1,2,3 , LIN1,2,3 & ITRIP)
VFLT
VCAO
VCA-
dVS/dt
PD
RthJA
TJ
TS
TL
FAULT Output Voltage
Operational Amplifier Output Voltage
Operational Amplifier Inverting Input Voltage
Allowable Offset Supply Voltage Transient
Package Power Dissipation @ TA ≤ +25°C (28 Lead DIP)
(28 Lead SOIC)
(44 Lead PLCC)
Thermal Resistance, Junction to Ambient (28 Lead DIP)
(28 Lead SOIC)
(44 Lead PLCC)
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
-0.3
VB1,2,3 - 25
VS1,2,3 - 0.3
-0.3
VCC - 25
-0.3
VSS - 0.3
VSS - 0.3
VSS - 0.3
VSS - 0.3
—
—
—
—
—
—
—
—
-55
—
625
VB1,2,3 + 0.3
VB1,2,3 + 0.3
25
VCC + 0.3
VCC + 0.3
(VSS + 15) or
(VCC + 0.3)
whichever is
lower
VCC + 0.3
VCC + 0.3
VCC + 0.3
50
1.5
1.6
2.0
83
78
63
150
150
300
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltages referenced to VS0. The VS offset rating is tested
with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figure 54.
Symbol
Definition
Min.
Max. Units
VB1,2,3
High Side Floating Supply Voltage
VS1,2,3 + 10 VS1,2,3 + 20
VS1,2,3
High Side Floating Offset Voltage
Note 1
600
VHO1,2,3
High Side Floating Output Voltage
VS1,2,3
VB1,2,3
VCC Low Side and Logic Fixed Supply Voltage
10 20
VSS Logic Ground
-5 5
VLO1,2,3
Low Side Output Voltage
0 VCC
VIN Logic Input Voltage (HIN1,2,3 , LIN1,2,3 & ITRIP)
VSS VSS + 5
VFLT
FAULT Output Voltage
VSS VCC
VCAO
Operational Amplifier Output Voltage
VSS VSS + 5
VCA-
Operational Amplifier Inverting Input Voltage
VSS VSS + 5
TA Ambient Temperature
-40 125
Note 1: Logic operational for VS of (VS0 - 5V) to (VS0 + 600V). Logic state held for VS of (VS0 - 5V) to (VS0 - VBS).
(Please refer to the Design Tip DT97-3 for more details).
Note 2: All input pins, CA- and CAO pins are internally clamped with a 5.2V zener diode.
V
°C
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