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National Semiconductor |
February 1986
DS1628 DS3628 Octal TRI-STATE MOS Drivers
General Description
The DS1628 DS3628 are octal Schottky memory drivers
with TRI-STATE outputs designed to drive high capacitive
loads associated with MOS memory systems The drivers’
output (VOH) is specified at 3 4V to provide additional noise
immunity required by MOS inputs A PNP input structure is
employed to minimize input currents The circuit employs
Schottky-clamped transistors for high speed A NOR gate of
two inputs DIS1 and DIS2 controls the TRI-STATE mode
Features
Y High speed capabilities
Typical 5 ns driving 50 pF 8 ns driving 500 pF
Y TRI-STATE outputs
Y High VOH (3 4V min)
Y High density
Eight drivers and two disable controls for TRI-STATE
in a 20-pin package
Y PNP inputs reduce DC loading on bus lines
Y Glitch-free power up down
Schematic and Connection Diagrams
Dual-In-Line Package
(Equivalent Input Output Circuit)
Truth Table
Disable Input
DIS 1
DIS 2
HH
HX
XH
LL
LL
H e high level
L e low level
X e don’t care
Z e high impedance (off)
Input
X
X
X
H
L
Top View
TL F 5875– 2
TL F 5875–1
Order Number
DS1628J DS3628J DS3628N
See NS Package Number J20A or N20A
Typical Application
Output
Z
Z
Z
L
H
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL F 5875
TL F 5875 –3
RRD-B30M115 Printed in U S A
http://www.Datasheet4U.com
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7 0V
Logical ‘‘1’’ Input Voltage
7 0V
Logical ‘‘0’’ Input Voltage
b1 5V
Storage Temperature Range
b65 C to a150 C
Maximum Power Dissipation at 25 C
Cavity Package
Molded Package
1667 mW
1832 mW
Lead Temperature (Soldering 10 seconds)
300 C
Derate cavity package 11 1 mW C above 25 C derate molded package
14 7 mW C above 25 C
Operating Conditions
Min
Supply voltage (VCC)
Temperature (TA)
DS1628
45
b55
DS3628
0
Max
55
a125
a70
Units
V
C
C
Electrical Characteristics (Notes 2 3)
Symbol
VIN(1)
VIN(0)
IIN(1)
IIN(0)
VCLAMP
VOH
VOL
VOH
VOL
IID
IOD
Hi-Z
ICC
Parameter
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Input Clamp Voltage
Logical ‘‘1’’ Output Voltage
(No Load)
Logical ‘‘0’’ Output Voltage
(No Load)
Logical ‘‘1’’ Output Voltage
(With Load)
Logical ‘‘0’’ Output Voltage
(With Load)
Logical ‘‘1’’ Drive Current
Logical ‘‘0’’ Drive Current
TRI-STATE Output Current
Power Supply Current
Conditions
VCC e 5 5V VIN e 5 5V
VCC e 5 5V VIN e 5 5V
VCC e 4 5V IIN e b18 mA
VCC e 4 5V IOH e b10 mA
VCC e 4 5V IOL e 10 mA
VCC e 4 5V IOH e b1 0 mA
VCC e 4 5V IOL e 20 mA
DS1628
DS3628
DS1628
DS3628
DS1628
DS3628
DS1628 DS3628
VCC e 4 5V VOUT e 0V (Note 6)
VCC e 4 5V VOUT e 4 5V (Note 6)
VOUT e 0 4V to 2 4V DIS1 or DIS2 e 2 0V
VCC e 5 5V One DIS Input e 3 0V
All Other Inputs e X Outputs at Hi-Z
DIS1 DIS2 e 0V Others e 3V
Outputs on
All Inputs e 0V Outputs Off
Min
20
34
35
25
27
b40
Typ
01
b180
b0 7
43
43
0 25
0 25
39
39
0 35
b150
150
01
90
70
25
Max
08
40
b400
b1 2
04
0 35
05
40
120
100
50
Units
V
V
mA
mA
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
Switching Characteristics (VCC e 5V TA e 25 C) (Note 6)
Symbol
Parameter
Conditions
Min Typ Max Units
tS a b
tSb a
tF
tR
tZL
Storage Delay Negative Edge
Storage Delay Positive Edge
Fall Time
Rise Time
Delay from Disable Input to Logical ‘‘0’’
Level (from High Impedance State)
(Figure 1 )
(Figure 1 )
(Figure 1 )
(Figure 1 )
CL e 50 pF
to GND
CL e 50 pF
CL e 500 pF
CL e 50 pF
CL e 500 pF
CL e 50 pF
CL e 500 pF
CL e 50 pF
CL e 500 pF
RL e 2 kX to VCC
(Figure 2 )
40 50
65 80
42 50
65 80
42 60
19 22
52 70
20 24
19 25
ns
ns
ns
ns
ns
tZH Delay from Disable Input to Logical ‘‘1’’ CL e 50 pF RL e 2 kX to GND
Level (from High Impedance State)
to GND
(Figure 2 )
13 20
ns
2
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