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MIC58P42BV 반도체 회로 부품 판매점

8-Bit Serial-Input Protected Latched Driver



Micrel Semiconductor 로고
Micrel Semiconductor
MIC58P42BV 데이터시트, 핀배열, 회로
MIC58P42
MIC58P42
Micrel
8-Bit Serial-Input Protected Latched Driver
General Description
The MIC58P42 serial-input latched driver is a high-voltage
(80V), high-current (500mA) integrated circuit comprised of
eight CMOS data latches, a bipolar Darlington transistor
driver for each latch, and CMOS control circuitry for the
common STROBE, CLOCK, SERIAL DATA INPUT, and
OUTPUT ENABLE functions. Similar to the MIC5842, addi-
tional protection circuitry supplied on this device includes
thermal shutdown, under voltage lockout (UVLO), and over-
current shutdown.
The bipolar/CMOS combination provides an extremely low-
power latch with maximum interface flexibility. The MIC58P42
has open-collector outputs capable of sinking 500 mA and
integral diodes for inductive load transient suppression with
a minimum output breakdown voltage rating of 80V (50V
sustaining). The drivers can be operated with a split supply,
where the negative supply is down to –20V and may be
paralleled for higher load current capability.
With a 5V logic supply, the MIC58P42 will typically operate at
better than 5MHz. With a 12V logic supply, significantly
higher speeds are obtained. The CMOS inputs are compat-
ible with standard CMOS, PMOS, and NMOS circuits. TTL
circuits may require pull-up resistors. By using the serial data
output, drivers may be cascaded for interface applications
requiring additional drive lines.
Each of these eight outputs has an independent over current
shutdown of 500 mA. Upon over-current detection, the
affected channel
ENABLE/RESET
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2µs will not activate current shutdown. Temperatures above
165°C will shut down the device. The UVLO circuit prevents
operation at low VDD; hysteresis of 0.5V is provided. See the
MIC59P60 for a similar device that additionally provides an
error flag output.
Features
• 3.3 MHz Minimum Data-Input Rate
• CMOS, PMOS, NMOS, and TTL Compatible
• Internal Pull-Up/Pull-Down Resistors
• Low Power CMOS Logic and Latches
• High Voltage (80V) Current-Sink Outputs
• Output Transient-Protection Diodes
• Single or Split Supply Operation
• Thermal Shutdown
• Under-Voltage Lockout
• Per-Output Over-Current Shutdown (500mA typical)
Ordering Information
Part Number Temperature Range Package
MIC58P42BN
–40°C to +85°C
18-Pin Plastic DIP
MIC58P42BV
–40°C to +85°C
20-Pin PLCC
MIC58P42BWM –40°C to +85°C
18-Pin Wide SOIC
Functional Diagram
Pin Configuration
(DIP and SOIC)
CLOCK 2
SERIAL
DATA IN
3
VSS 4
UVLO
8-BIT SERIAL–PARALLEL SHIFT REGISTER
LATCHES
MOS
BIPOLAR
6 SERIAL DATA OUT
5 VDD
7 STROBE
8 OUTPUT
ENABLE/RESET
THERMAL
SHUTDOWN
ILIMIT
10 18 17 16 15 14 13 12 11
SUB 1
9
K OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
VEE
VEE
CLOCK
1
SUB
2
SERIAL DATA IN 3
VSS 4
VDD 5
SERIAL DATA OUT 6
STROBE 7
OUTPUT
ENABLE/RESET
8
VEE 9
SUB
UVLO
18 OUT1
17 OUT2
16 OUT3
15 OUT4
14 OUT5
13 OUT6
12 OUT7
11 OUT8
10 K
I LIMIT
THERMAL
SHUTDOWN
October 1998
7-49
7


MIC58P42BV 데이터시트, 핀배열, 회로
MIC58P42
PLCC Pin Configuration
NC 4
VSS 5
VDD 6
SERIAL DATA OUT 7
NC 8
32
1 20 19
18 OUT 3
17 OUT 4
MIC58P42BV 16 OUT 5
15 OUT 6
14 OUT 7
9 10 11 12 13
Micrel
Absolute Maximum Ratings (Note 1, 2)
at 25°C Free-Air Temperature and VSS = 0V
Output Voltage
Output Voltage, VCE(SUS) (Note 1)
Logic Supply Voltage Range, VDD
VDD with Reference to VEE
Emitter Supply Voltage (Substrate), VEE
Input Voltage Range, VIN
Package Power Dissipation, PD
MIC58P42BN
Derate above TA = +25°C
MIC58P42BV
Derate above TA = +25°C
MIC58P42BWM
Derate above TA = +25°C
Operating Temperature Range, TA
Storage Temperature Range, TS
80V
50V
4.5V to 15V
25V
–20V
–0.3V to VDD + 0.3V
1.82W
18mW/°C
1.4W
14mW/°C
1.2W
12mW/°C
–55°C to +125°C
–65°C to +150°C
Note 1: For Inductive load applications.
Note 2: CMOS devices have input-static protection but are susceptible to
damage when exposed to extremely high static electrical
charges.
Typical Input Circuits
Typical Output Driver
STROBE
OUTPUT
ENABLE
V DD
V SS
CLOCK
SERIAL
DATA IN
V DD
V SS
K
OUT N
3K
V EE
SUB
Pin Description
Pin
(DIP & S.O.)
1,9
2
3
4
5
6
7
8
10
11—18
Name
Description
VEE
CLOCK
Substrate. Most Negative voltage in the system connects here.
Serial Data Clock. A CLEAR input must also be clocked into the latches.
SERIAL DATA IN Serial Data Input pin.
VSS
VDD
SERIAL DATA OUT
Logic reference (Ground) pin.
Logic Positive Supply voltage.
Serial Data Output pin. (Flow–through).
STROBE
Output Strobe pin. Loads output latches when high. Strobe is needed to clear latch.
OUTPUT
ENABLE/RESET
When Low, Outputs are active. When High, device is reset from a fault condition.
K Transient suppression diode's cathode common pin.
OUTPUT N
Open Collector outputs 8 through 1.
7-50
October 1998




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MIC58P42BV driver

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