D5V0P4UR6SO 반도체 회로 부품 판매점
4 CHANNEL LOW CAPACITANCE TVS DIODE ARRAY
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 Diodes |
D5V0P4UR6SO
4 CHANNEL LOW CAPACITANCE TVS DIODE ARRAY
Product Summary
VBR (Min)
4.5V
IPP (Max)
45A
CT (Typ)
2.1pF
Description
The D5V0P4UR6SO is a high-performance device suitable for
protecting four high-speed I/Os. These devices are assembled in
SOT26 package and have high ESD surge capability and low
capacitance.
Applications
Typically used at high-speed ports such as USB 2.0, IEEE1394
(Firewire®, iLink™), Serial ATA, DVI, HDMI and PCI.
SOT26
Features
Low Clamping Voltage: Typical 7.5V at 12A 100ns, TLP, I/O to
VSS; Typical 5.8V at 12A 100ns, TLP, VCC to VSS
IEC 61000-4-2 (ESD): Air – ±30kV, Contact – ±30kV
IEC 61000-4-4 (EFT): ±80A (5/50ns)
IEC 61000-4-5 (Lighting): 20A, I/O to VSS; 45A, VCC to VSS
TLP Dynamic Resistance: 0.15Ω, I/O to VSS; 0.07Ω, VCC to VSS
Low Channel Input Capacitance of 2.1pF Typical
4 Channels of ESD Protection
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Mechanical Data
Case: SOT26
Moisture Sensitivity: Level 1 per J-STD-020
Terminal Connections: See Schematic
Terminals – Finish – Matte Tin Pleated Leadframe.
Solderable per MIL-STD-202, Method 208
Weight: 0.016 grams (Approximate)
Top View
Device Schematic
Ordering Information (Note 4)
Product
D5V0P4UR6SO-7
Compliance
Standard
Marking
DE1
Reel Size (inches)
7
Tape Width (mm)
8
Quantity per Reel
3,000/Tape & Reel
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
4. For packaging details, go to our website at http://www.diodes.com/products/packages.html.
Marking Information
DAE117
DE1 = Product Type Marking Code
YM = Date Code Marking
Y = Year (ex: D = 2016)
M = Month (ex: 9 = September)
Note: “ ” Represents Internal Code
Date Code Key
Year
Code
Month
Code
2016
D
Jan Feb
12
2017
E
Mar Apr
34
2018
F
May
5
Jun
6
2019
G
Jul Aug
78
2020
H
Sep Oct
9O
2021
I
Nov Dec
ND
FireWire is a registered trademark of Apple Computer, Inc.
iLink is a trademark of CEM Corporation.
D5V0P4UR6SO
Document number: DS38235 Rev. 1 - 2
1 of 5
www.diodes.com
May 2016
© Diodes Incorporated
D5V0P4UR6SO
Maximum Ratings (@TA = +25°C, unless otherwise specified.)
Characteristic
Peak Pulse Current, per IEC 61000-4-5
Peak Pulse Current, per IEC 61000-4-5
Peak Pulse Power, per IEC 61000-4-5
Operating Supply Voltage (DC)
ESD Protection – Contact Discharge, per IEC 61000-4-2
ESD Protection – Air Discharge, per IEC 61000-4-2
Operating Temperature
Storage Temperature
Symbol
IPP
IPP
PPP
VDC
VESD_CONTACT
VESD_AIR
TOP
TSTG
Value
20
45
180
3.6
±30
±30
-55 to +85
-55 to +150
Unit
A
A
W
V
kV
kV
°C
°C
Conditions
I/O to VSS, 8/20μs
VCC to VSS, 8/20μs
I/O to VSS, 8/20μs
VCC to VSS
I/O to VSS, VCC to VSS
I/O to VSS, VCC to VSS
—
—
Thermal Characteristics
Characteristic
Power Dissipation Typical (Note 5)
Thermal Resistance, Junction to Ambient Typical (Note 5)
Symbol
PD
RθJA
Value
300
417
Unit
mW
°C/W
Electrical Characteristics (@TA = +25°C, unless otherwise specified.)
Characteristic
Reverse Working Voltage
Reverse Leakage Current (Note 6)
Channel Leakage Current (Note 6)
Reverse Breakdown Voltage
Forward Clamping Voltage
Reverse Clamping Voltage (Note 7)
ESD Clamping Voltage
Dynamic Resistance
Channel Input Capacitance
Symbol
VRWM
ILEAK
ICH-LEAK
VBR
VF
VC_5A
VESD
RDIF
CI/O
Variation of Channel Input Capacitance
CI/O
Min Typ
——
——
——
4.5 —
— 0.8
—6
— 4.8
— 7.5
— 5.8
— 0.15
— 0.07
— 2.1
— 2.4
— 0.05
— 0.04
Max
3.3
5
1
7
1.2
—
—
—
—
—
—
2.5
3.0
0
—
—
Unit
V
μA
μA
V
V
V
V
V
Ω
pF
pF
pF
pF
Test Conditions
VCC to VSS
VCC = 3.3V, VCC to VSS
VI/O = 3.3V, I/O to VSS
IBR = 1mA, VCC to VSS
IF = 15mA, VSS to VCC
IPP = 5A, I/O to VSS, 8/20μs
IPP = 5A, VCC to VSS, 8/20μs
TLP, 12A, tP = 100ns, I/O to VSS
TLP, 12A, tP = 100ns, VCC to VSS
TLP, 12A, tP = 100ns, I/O to VSS
TLP, 12A, tP = 100ns, VCC to VSS
VI/O = 1.65V, VCC = 3.3V, f = 1MHz
VI/O = 1.65V, VCC = floated, f = 1MHz
VSS = 0V, I/O = 1.65V, VCC = 3.3V, f = 1MHz,
I/O_x to VSS – I/O_y to VSS
VSS = 0V, I/O = 1.65V, VCC = floated, f = 1MHz,
I/O_x to VSS – I/O_y to VSS
Notes:
5. Device mounted on FR-4 PCB pad layout (2oz copper) as shown on Diodes, Inc. website at http://www.diodes.com/package-outlines.html.
6. Short duration pulse test used to minimize self-heating effect.
7. Clamping voltage value is based on an 8x20µs peak pulse current (IPP) waveform.
D5V0P4UR6SO
Document number: DS38235 Rev. 1 - 2
2 of 5
www.diodes.com
May 2016
© Diodes Incorporated
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D5V0P4UR6SO diode
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