SN54LS93 반도체 회로 부품 판매점
4-BIT BINARY COUNTER
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 Motorola Semiconductors |
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di-
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary
• Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
LOADING (Note a)
HIGH
LOW
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
Clock (Active LOW going edge) Input to
÷2 Section
Clock (Active LOW going edge) Input to
÷5 Section (LS90), ÷6 Section (LS92)
Clock (Active LOW going edge) Input to
÷8 Section (LS93)
Master Reset (Clear) Inputs
Master Set (Preset-9, LS90) Inputs
Output from ÷2 Section (Notes b & c)
Outputs from ÷5 (LS90), ÷6 (LS92),
÷8 (LS93) Sections (Note b)
0.5 U.L.
1.5 U.L.
0.5 U.L.
2.0 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b. Temperature Ranges.
c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
LS90
67
12
MS
14 CP0
1 CP1
MR Q0 Q1 Q2 Q3
12
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PINS 4, 13
LOGIC SYMBOL
LS92
14 CP0
1 CP1
MR Q0 Q1 Q2 Q3
12
6 7 12 11 9 8
VCC = PIN 5
GND = PIN 10
NC = PINS 2, 3, 4, 13
FAST AND LS TTL DATA
5-1
SN54/74LS90
SN54/74LS92
SN54/74LS93
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
LS93
14 CP0
1 CP1
MR Q0 Q1 Q2 Q3
12
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PIN 4, 6, 7, 13
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
LOGIC DIAGRAM
6
MS1
MS2 7
14
CP0
1
CP1
2
MR1
MR2 3
J SD Q
CP
K CD Q
12
Q0
LS90
J SD Q
CP
K CD Q
J SD Q
CP
K CD Q
R SD Q
CP
S CD Q
98
Q1 Q2
11
Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
LOGIC DIAGRAM
LS92
14
CP0
JQ
CP
K CD Q
JQ
CP
K CD Q
JQ
CP
K CD Q
JQ
CP
K CD Q
1
CP1
6
MR1
MR2 7
12
Q0
11
Q1
9
Q2
8
Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
LOGIC DIAGRAM
LS93
14
CP0
JQ
CP
K CD Q
JQ
CP
K CD Q
JQ
CP
K CD Q
JQ
CP
K CD Q
1
CP1
2
MR1
MR2 3
12
Q0
9 8 11
Q1 Q2 Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
FAST AND LS TTL DATA
5-2
CONNECTION DIAGRAM
DIP (TOP VIEW)
CP1 1
MR1 2
MR2 3
NC 4
VCC 5
MS1 6
MS2 7
14 CP0
13 NC
12 Q0
11 Q3
10 GND
9 Q1
8 Q2
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM
DIP (TOP VIEW)
CP1 1
NC 2
NC 3
NC 4
VCC 5
MR1 6
MR2 7
14 CP0
13 NC
12 Q0
11 Q1
10 GND
9 Q2
8 Q3
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM
DIP (TOP VIEW)
CP1 1
MR1 2
MR2 3
NC 4
VCC 5
NC 6
NC 7
14 CP0
13 NC
12 Q0
11 Q3
10 GND
9 Q1
8 Q2
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
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제조업체: Motorola Semiconductors
( motorola )
SN54LS93 data
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