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M2V64S40BTP-8 반도체 회로 부품 판매점

64M bit Synchronous DRAM



Mitsubishi 로고
Mitsubishi
M2V64S40BTP-8 데이터시트, 핀배열, 회로
SDRAM (Rev.1.2)
Apr. '99
64M bit Synchronous DRAM
MITSUBISHI LSIs
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
DESCRIPTION
The M2V64S20BTP is organized as 4-bank x 4194304-word x 4-bit, M2V64S30BTP is
organized as 4-bank x 2097152-word x 8-bit, and M2V64S40BTP is organized as 4-bank x
1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are
referenced to the rising edge of CLK. The M2V64S20BTP, M2V64S30BTP, M2V64S40BTP
achieve very high speed data rate up to 125MHz, and are suitable for main memory or
graphic memory in computer systems.
FEATURES
- Single 3.3v ± 0.3v power supply
- Clock frequency 125MHz /100MHz
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/Full Page (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
- Burst Write / Single Write (programmable)
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A9 (x4), A0-A8(x8), A0-A7(x16)
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
M2V64S20BTP
M2V64S30BTP
M2V64S40BTP
-7, -7L
-8, -8L
-8A
-10, -10L
Max.
Frequency
CLK Access
Time
100MHz(CL2)
6ns
100MHz(CL3)
6ns
125MHz
6ns
100MHz
8ns
MITSUBISHI ELECTRIC
1


M2V64S40BTP-8 데이터시트, 핀배열, 회로
SDRAM (Rev.1.2)
Apr. '99
64M bit Synchronous DRAM
MITSUBISHI LSIs
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
PIN CONFIGURATION (TOP VIEW)
M2V64S20BTP
M2V64S30BTP
M2V64S40BTP
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 Vss
Vss
53 DQ15
52 VssQ
DQ7
VssQ
51 DQ14
NC
50 DQ13
49 VddQ
48 DQ12
DQ6
VddQ
NC
47 DQ11
46 VssQ
45 DQ10
DQ5
VssQ
NC
44 DQ9
DQ4
43 VddQ
VddQ
42 DQ8
NC
41 Vss
Vss
40 NC
NC
39 DQMU DQM
38 CLK
37 CKE
36 NC
CLK
CKE
NC
35 A11
A11
34 A9
A9
33 A8
A8
32 A7
A7
31 A6
A6
30 A5
A5
29 A4
28 Vss
A4
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-3(x4), DQ0-7(x8), DQ0-15(x16)
DQM (x4, x8) ,DQML/U (x16)
A0-11
BA0,1
Vdd
VddQ
Vss
VssQ
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Output Disable/ Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
2




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