CY7C0241 판매점 - 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM

CY7C0241 반도체 회로 부품 판매점

4K x 16/18 and 8K x 16/18 Dual-Port Static RAM

Cypress Semiconductor

CY7C024/024A/0241

CY7C025/0251

4K x 16/18 and 8K x 16/18 Dual-Port

Static RAM with SEM, INT, BUSY

Features

■ True dual-ported memory cells, which allow simultaneous

reads of the same memory location

■ 4K x 16 organization (CY7C024/024A[1])

■ 4K x 18 organization (CY7C0241)

■ 8K x 16 organization (CY7C025)

■ 8K x 18 organization (CY7C0251)

■ 0.65 micron CMOS for optimum speed and power

■ High speed access: 15 ns

■ Low operating power: ICC = 150 mA (typ)

■ Fully asynchronous operation

■ Automatic power down

■ Expandable data bus to 32/36 bits or more using Master/Slave

chip select when using more than one device

■ On-chip arbitration logic

■ Semaphores included to permit software handshaking

between ports

■ INT flag for port-to-port communication

■ Separate upper-byte and lower-byte control

■ Pin select for Master or Slave

■ Available in 84-pin (Pb-free) PLCC, 84-pin PLCC, 100-pin

(Pb-free) TQFP, and 100-pin TQFP

Functional Description

The CY7C024/024A/0241 and CY7C025/0251 are low power

CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Various

arbitration schemes are included on the CY7C024/ 0241 and

CY7C025/0251 to handle situations when multiple processors

access the same piece of data. Two ports are provided,

permitting independent, asynchronous access for reads and

writes to any location in memory. The CY7C024/ 0241 and

CY7C025/0251 can be used as standalone 16 or 18-bit dual-port

static RAMs or multiple devices can be combined to function as

a 32-/36-bit or wider master/ slave dual-port static RAM. An M/S

pin is provided for implementing 32-/36-bit or wider memory

applications without the need for separate master and slave

devices or additional discrete logic. Application areas include

interprocessor/multiprocessor designs, communications status

buffering, and dual-port video/graphics memory.

Each port has independent control pins: Chip Enable (CE), Read

or Write Enable (R/W), and Output Enable (OE). Two flags are

provided on each port (BUSY and INT). BUSY signals that the

port is trying to access the same location currently being

accessed by the other port. The Interrupt Flag (INT) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from one

port to the other to indicate that a shared resource is in use. The

semaphore logic is comprised of eight shared latches. Only one

side can control the latch (semaphore) at any time. Control of a

semaphore indicates that a shared resource is in use. An

automatic power down feature is controlled independently on

each port by a chip select (CE) pin.

The CY7C024/024A/0241 and CY7C025/0251 are available in

84-pin Pb-free PLCCs, 84-pin PLCCs (CY7C024 and CY7C025

only), 100-pin Pb-free Thin Quad Plastic Flatplack (TQFP), and

100-pin Thin Quad Plastic Flatpack.

Note

1. CY7C024 and CY7C024A are functionally identical.

Cypress Semiconductor Corporation • 198 Champion Court

Document #: 38-06035 Rev. *D

• San Jose, CA 95134-1709 • 408-943-2600

Revised December 09, 2008

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CY7C024/024A/0241

CY7C025/0251

Logic Block Diagram

OE L

R/WR

UBR

LBR

CER

OE R

[4]

I/O 8L – I/O 15L

I/O

–

I/O

[3]

[2]

BUSYL

(CY7C025/0251) A12L

A11L

A0L

Pin Configurations

R/W L

SEM L

INT L

I/O

CONTROL

I/O

CONTROL

ADDRESS

DECODER

MEMORY

ARRAY

ADDRESS

DECODER

CE L

OE L

UB L

LB L

INTERRUPT

SEMAPHORE

ARBITRATION

M/S

CE R

OE R

UB R

LB R

Figure 1. 84-Pin PLCC (Top View)

I/O8R – I/O15R[4]

I/O

0R–

I/O

[3]

[2]

BUSYR

A12R (CY7C025/0251)

A11R

A 0R

R/W R

SEM R

INTR

I/O8L

I/O9L

I/O10L

I/O11L

I/O12L

I/O13L

GND

I/O14L

I/O15L

VCC

GND

I/O0R

I/O1R

I/O2R

VCC

I/O3R

I/O4R

I/O5R

I/O6R

I/O7R

I/O8R

11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

12 73

13 72

14 71

15 70

16 69

17 68

18 67

21 CY7C024/024A/025

24 62

25 61

26 60

27 59

28 58

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

A7L

A6L

A5L

A4L

A3L

A2L

A1L

A0L

INTL

BUSYL

GND

M/S

BUSYR

INTR

A0R

A1R

A2R

A3R

A4R

A5R

A6R

Notes

2. BUSY is an output in master mode and an input in slave mode.

3. I/O0 –I/O8 on the CY7C0241/0251.

4. I/O9 –I/O17 on the CY7C0241/0251.

5. A12L on the CY7C025/0251.

6. A12R on the CY7C025/0251.

Document #: 38-06035 Rev. *D

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제조업체: Cypress Semiconductor

( cypress )

CY7C0241 data

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CY7C0241 반도체 회로 부품 판매점

4K x 16/18 and 8K x 16/18 Dual-Port Static RAM

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일반적인 전자부품 판매점

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