NT5TU64M16GG-BE 반도체 회로 부품 판매점
1Gb DDR2 SDRAM
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 Nanya |
NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Feature
CAS Latency Frequency
Speed Bins
-3C/3CI
(DDR2-667-CL5)
-AC/ACI/ACL
(DDR2-800-CL5)
-BE
(DDR2-1066-CL7)
Parameter
Min. Max. Min. Max.
Min.
Max.
Clock Frequency 125 333 125 400 125 533
tRCD
15 - 12.5 - 12.5 -
tRP 15 - 12.5 - 12.5 -
tRC 60 - 57.5 - 57.5 -
tRAS
40 70K 40 70K 40 70K
tCK(Avg.)@CL3 5 8 5 8 5 8
tCK(Avg.)@CL4 3.75 8 3.75 8
3.75
8
tCK(Avg.)@CL5 3 8 2.5 8 2.5 8
tCK(Avg.)@CL6
-
- 2.5 8 2.5 8
tCK(Avg.)@CL7
-
-
-
-
1.875
8
*The timing specification of high speed bin is backward compatible with low speed bin
-BD
(DDR2-1066-CL6)
Min.
Max.
125 533
11.25
-
11.25
-
56.25
-
40 70K
58
3.75 8
2.5 8
1.875
8
1.875
8
Units
tCK(Avg.)
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
VDD=VDDQ=1.8V ± 0.1V Voltage
Support Industrial grade temperature
JEDEC standard 1.8V I/O (SSTL_18 compatible)
(–40°C≦TC≦ 95°C; –40°C≦TA≦ +85°C)
8 internal memory banks
Programmable CAS Latency:
Support automotive grade 3 temperature
(–40°C≦TC≦ 95°C; –40°C≦TA≦ +85°C)
3, 4, 5 (-3C/3CI, -AC/ACI/ACL, -BE, -BD);
1KB page size for x8
6 (-AC/ACI/ACL, -BE, -BD);
2KB page size for x16
7 (-BE, -BD)
Strong and Weak Strength Data-Output Driver
Programmable Additive Latency: 0, 1, 2, 3, 4 5
Auto-Refresh and Self-Refresh
Write Latency = Read Latency -1
Programmable Burst Length:
Power Saving Power-Down modes
7.8 µs max. Average Periodic Refresh Interval
4 and 8 Programmable Sequential / Interleave Burst
RoHS Compliance and Halogen Free
OCD (Off-Chip Driver Impedance Adjustment)
AEC-Q100 for NT5TU128M8GE – ACI
ODT (On-Die Termination)
PPAP submission for NT5TU128M8GE – ACI
4n-bit prefetch architecture
Data-Strobes: Bidirectional, Differential
Packages: 60-Ball BGA for x8 components
84-Ball BGA for x16 components
REV 2.0
02/2013
1
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Description
The 1giga bit (1Gb) Double-Data-Rate-2 (DDR2) DRAMs is a high-speed CMOS Double Data Rate 2 SDRAM
containing 1,073,741,824 bits. It is internally configured as an octal-bank DRAM.
The 1Gb chip is organized as 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These synchronous devices
achieve high speed double-data-rate transfer rates of up to 1066 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write
latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance
adjustment and (5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended
DQS or differential DQS pair in a source synchronous fashion. A13 bit address bus for x8 organized components and A
12 bit address bus for x16 component is used to convey row, column, and bank address devices.
These devices operate with a single 1.8V ± 0.1V power supply and are available in BGA packages.
REV 2.0
02/2013
2
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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