CY7C0832V 반도체 회로 부품 판매점
Synchronous Dual-Port RAM
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 Cypress Semiconductor |
CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18
Synchronous Dual-Port RAM
PRELIMINARY
CY7C0837V
CY7C0830V/CY7C0831V
CY7C0832V/CY7C0833V
FLEx18TM 3.3V 32K/64K/128K/256K/512K x 18
Synchronous Dual-Port RAM
Features
Functional Description
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• Synchronous pipelined operation
• Family of 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit
devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 144-ball FBGA (13 mm × 13 mm) (1.0 mm pitch)
• 120TQFP (14 mm x 14 mm x 1.4 mm)
• Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
expansion
The FLEx18 family includes 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit
and 9-Mbit pipelined, synchronous, true dual-port static RAMs
that are high-speed, low-power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location
by more than one port at the same time is undefined. Registers
on control, address, and data lines allow for minimal set-up
and hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0833V device in this family has limited features.
Please see Address Counter and Mask Register
Operations[15] on page 6 for details.
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
Max. Access Time - clock to Data (ns)
Typical operating current (mA)
Package
512-Kbit
(32K x 18)
CY7C0837V
167
4.0
225
144 FBGA
1-Mbit
(64K x 18)
CY7C0830V
167
4.0
225
120 TQFP
144 FBGA
2-Mbit
(128K x 18)
CY7C0831V
167
4.0
225
120 TQFP
144 FBGA
4-Mbit
(256K x 18)
CY7C0832V
167
4.0
225
120 TQFP
144 FBGA
9-Mbit
(512K x 18)
CY7C0833V
133
4.7
270
144 FBGA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06059 Rev. *K
July 06, 2004
Logic Block Diagram[1]
OEL
R/WL
B0L
B1L
CE0L
CE1L
PRELIMINARY
CY7C0837V
CY7C0830V/CY7C0831V
CY7C0832V/CY7C0833V
OER
R/WR
B0R
B1R
CE0R
CE1R
DQ9L–DQ17L
DQ0L–DQ8L
9
9
I/O
Control
I/O
Control
9 DQ9R–DQ17R
9
DQ0R–DQ8R
A0L–A18L
CNT/MSKL
ADSL
CNTENL
CNTRSTL
CLKL
CNTINTL
19
INTL
Addr.
Read
Back
Mask Register
Counter/
Address
Register
Mirror Reg
True
Dual-Ported
RAM Array
Address
Decode
Address
Decode
Interrupt
Logic
MRST
Reset
Logic
TMS
TDI
TCK
JTAG
Addr.
Read
Back
Mask Register
Counter/
Address
Register
Mirror Reg
TDO
Interrupt
Logic
19 A0R–A18R
CNT/MSKR
ADS
CNTEN
CNTRSTR
CLKR
CNTINTR
INTR
Note:
1. CY7C0837V has 15 address CY7C0830V has 16 address bits, CY7C0831V has 17 address bits, CY7C0832V has 18 address bits and CY7C0833V has 19
address bits
Document #: 38-06059 Rev. *K
Page 2 of 28
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